IDT 89HPES34H16, User Manual, Page: 179 / 182

IDT JTAG Boundary Scan
PES34H16 User Manual 10 - 7 October 30, 2008
Notes
Figure 10.5 Diagram of Output Enable Cell
The bidirectional cells are composed of only two boundary scan cells. They contain one output enable
cell and one capture cell, which contains only one register. The input to this single register is selected via a
mux that is selected by the output enable cell when EXTEST is disabled. When the Output Enable Cell is
driving a high out to the pad (which enables the pad for output) and EXTEST is disabled, the Capture Cell
will be configured to capture output data from the core to the pad.
However, in the case where the Output Enable Cell is low (signifying a tri-state condition at the pad) or
EXTEST is enabled, the Capture Cell will capture input data from the pad to the core. The configuration is
shown graphically in Figure 10.5.
Instruction Register (IR)
The Instruction register allows an instruction to be shifted serially into the device at the rising edge of
JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be
accessed, or both. The instruction shifted into the register is latched at the completion of the shifting
process, when the TAP controller is at the Update-IR state.
The Instruction register contains six shift-register-based cells that can hold instruction data. This register
is decoded to perform the following functions:
– To select test data registers that may operate while the instruction is current. The other test data
registers should not interfere with chip operation and selected data registers.
– To define the serial test data register path used to shift data between JTAG_TDI and JTAG_TDO
during data register scanning.
The Instruction register is comprised of 6 bits to decode instructions, as shown in Table 10.3.
D Q
D
Q
Data from core
shift_dr
MU
X
D Q D
Q
clock_dr
shift_dr
update_dr
MUX
MU
X
MU
X
OEN to pad
I/O pin
Output enable from core
EXTEST
EXTEST
Data from previous cell
To next cell