IDT 89HPES34H16, User Manual, Page: 100 / 182

IDT Configuration Registers
PES34H16 User Manual 9 - 8 October 30, 2008
Notes
Downstream Ports (Ports 1 through 15)
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
0x000 Word Px_VID VID - Vendor Identification Register (0x000) on page 9-11
0x002 Word Px_DID DID - Device Identification Register (0x002) on page 9-12
0x004 Word Px_PCICMD PCICMD - PCI Command Register (0x004) on page 9-12
0x006 Word Px_PCISTS PCISTS - PCI Status Register (0x006) on page 9-13
0x008 Byte Px_RID RID - Revision Identification Register (0x008) on page 9-14
0x009 3 Bytes Px_CCODE CCODE - Class Code Register (0x009) on page 9-14
0x00C Byte Px_CLS CLS - Cache Line Size Register (0x00C) on page 9-14
0x00D Byte Px_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-15
0x00E Byte Px_HDR HDR - Header Type Register (0x00E) on page 9-15
0x00F Byte Px_BIST BIST - Built-in Self Test Register (0x00F) on page 9-15
0x010 DWord Px_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-15
0x014 DWord Px_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-15
0x018 Byte Px_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 9-15
0x019 Byte Px_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 9-16
0x01A Byte Px_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 9-16
0x01B Byte Px_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page 9-16
0x01C Byte Px_IOBASE IOBASE - I/O Base Register (0x01C) on page 9-16
0x01D Byte Px_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 9-17
0x01E Word Px_SECSTS SECSTS - Secondary Status Register (0x01E) on page 9-17
0x020 Word Px_MBASE MBASE - Memory Base Register (0x020) on page 9-18
0x022 Word Px_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 9-18
0x024 Word Px_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page 9-
18
0x026 Word Px_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page 9-19
0x028 DWord Px_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028) on
page 9-19
0x02C DWord Px_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C) on
page 9-19
0x030 Word Px_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-19
0x032 Word Px_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 9-20
0x034 Byte Px_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 9-20
0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on
page 9-20
Table 9.3 Downstream Ports 1 through 15 Configuration Space Registers (Part 1 of 4)