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PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
9. Error
Handling
Topics discussed include the following:
•
•
“PCIe as Originating Interface”
•
“PCI as Originating Interface”
•
•
•
9.1
Overview
This chapter discusses how the PEB383 handles errors that occur during the processing of upstream
and downstream transactions. For all errors that are detected by the bridge, it sets the appropriate Error
Status bits – PCI Error bit(s) and PCIe Error status bit(s) – and generates an error message on PCIe, if
enabled.
Each error condition has an error severity level programmable by software, and a corresponding error
message generated on PCIe. Each detected error condition has a default error severity level (fatal or
non-fatal) and, when enabled, has a corresponding error message generated on PCIe. The error severity
level is software programmable.
PCIe link error message generation is controlled by the following bits:
•
SERR_EN in the
“PCI Bridge Control and Interrupt Register”
•
FTL_ERR_EN in the
“PCIe Device Control and Status Register”
•
NFTL_ERR_EN in the
“PCIe Device Control and Status Register”
•
COR_ERR_EN in the
“PCIe Device Control and Status Register”
ERR_FATAL PCIe messages are enabled for transmission if either of the following bits is set:
SERR_EN in
“PCI Control and Status Register”