82V3911 WAN PLL
EVALUATION BOARD USER’S GUIDE
4
REVISION 1 1/30/15
1.1
ANNOTATION FOR FIGURE-1
[1] Output clock 1 - 5
[2] 82V3911 chip
[3] Switch SW5: The function of this switch is described in
Table-1
.
[4] Crystal oscillator Master Clock
[5] +5 V DC power supply
[6] +3.3 V power supply for test purpose
[7] +5 V power supply for test purpose
[8] Crystal oscillator for APLL1 and APLL2
[9] OSCI: master clock input
[11] 8 kHz or 1pps frame synchronization output
[12] 2 kHz multi-frame or 1pps frame synchronization output
[13] Output clock 6 (differential)
[14] Output clock 7 (differential)
[15] Output clock 8 (differential)
[16] Output clock 9 (differential)
[17] Input clock to APLL1 (differential)
[18] Input clock to APLL2 (differential)
[19] Input clock 1 (differential)
[20] Input clock 2 (differential)
[21] Input clock 3-6
[22] External frame sync 1 and 2 input
[23] USB communication port
[24] DPLL1 and DPLL2 DPLL lock indicator
[25] Reset button: Press to reset all devices on the board
Table-1 Switch SW5 Function Description
Switch
Function Description
SW5-2
SDH/SONET selection
Off: SDH
On: SONET
SW5-3
not used
SW5-4~6
not used
SW5-7
I2C_AD1
Off: "0"
On: "1"
SW5-8
I2C_AD2
I2C_AD1 and I2C_AD2 pins
are the address bus of the
microprocessor interface.
Off: "0"
On: "1"
