82V3911 WAN PLL
REVISION 1 1/30/15
13
EVALUATION BOARD USER’S GUIDE
2.6
DPLL2 PATH CONFIGURATION
2.6.1
DPLL2 INPUT SELECTOR
Click on “DPLL2 Input Selector” or select “Window > DPLL2 Input”. The
following dialog box pops out, allowing users to select an input to the
DPLL2.
Figure-18 DPLL2 Input Selector Dialog Box
2.6.2
DPLL2 DPLL
Click on “DPLL2 PFD & LP” or select “Window > DPLL2”. The DPLL2
dialog box pops out as shown in
Figure-19
. This dialog box allows users to
configure the DPLL2.
Figure-19 DPLL2 Dialog Box
Note: Before opening this dialog box, users must select the DPLL2
path (see
2.2.3 DPLL1/ DPLL2 Path Selection
), otherwise the DPLL2
coarse/fine phase detector can not be configured.
click to read register R51 and refresh the display of this dialog
DPLL2 input clock selection when DPLL2 locks independently from DPLL1
DPLL2 lock/not lock to
(checked: lock to T0)
lock to 8k or 77.76M
(checked: 8k)
register address
and bits
click to exit this dialog
DPLL2 operating mode selection
register address and bits
