3 - 9
(2) RX 2ND LO CIRCUIT
The signal from the hybrid divider passes through the
attenuator (R802, R803), and is then applied to the
amplifier (Q801). The signal passes through the attenuator
(R805–R807), and is then applied to the mixer circuit (D821)
to mix with TX 3rd LO signal. The mixed signal passes
through the attenuator (R831–R833) and bandpass filter
(FI831), and is then applied to the amplifier (Q831). The
signal passes through the attenuator (R836–R838), and is
then applied to the LO (Q1651) and buffer (IC1651, pins 9,
10) amplifiers. The amplified signal is applied to the buffer
amplifier (IC1651, pins 1, 2), and is then applied to the 2nd
mixer circuit (IC1501, pin 1) as 2nd LO signal.
A part of amplified signal from buffer amplifier (IC1651, pin
8) passes through the 90 degrees phase inversion circuit
(L1652, C1655 and C1656), and is then amplified at the
buffer amplifier (IC1651, pins 4, 5). The amplified signal is
applied to the 2nd mixer circuit (IC1502, pin 1) as 2nd LO
signal.
• TX 3RD LO CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(Q652) via the “40M” line, and is then applied to the DDS
IC (IC651, pin 7) as the system clock signal. The signals
which are output from pins 13–22 are applied to the D/A
convertor (R661–R671, R673–R681), and then passes
through the low-pass filter (L681, L682, C680–C685)
to suppress more than 0.5 MHz signals. The signal is
amplified at the buffer amplifier (Q680), and passes through
the attenuator (R690–R692). The signal is applied to the
TX 3rd mixer circuit (MAIN unit; IC503, pin 1) via the J681.
3-3-4 RXPLL-B CIRCUIT (RXPLL-B UNIT)
The 10 MHz oscillated signal from the OSC unit is applied
to the amplifier (Q30) via the J10, and is then amplified
at the quadrupler (Q702) to produce 40 MHz reference
signal. The amplified signal passes through the attenuator
(R708–R710), and is then applied to the 1st LO, 2nd LO,
DSP system clock and scope unit system clock circuits,
respectively.
• 1ST LO CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(Q104) via the “40M” line, and is then applied to the DDS
IC (IC101, pin 88) as the system clock signal. The output
signals from pins 7–20 pass through the D/A convertor
(R110–R133). The converted signal passes through the
ceramic filter (FI101) to pass the 10.7 MHz signal, and is
then applied to the amplifier (IC102, pin 2). The amplified
signal is applied to the DDS IC (IC101, pin 47) again, and
is then applied to the phase detector section of the DDS
IC. The signal which outputs from the DDS IC (IC101, pin
56) passes through the loop filter (D152–D154, L151, C152
–C155), and is then applied to the oscillator circuit (Q150).
The circuit oscillates 10.5813219–10.7408384 MHz signal.
The oscillated signal is applied to the amplifier (Q151), and
is then applied to the PLL IC (IC201).
A part of the oscillated signal is fed back to the DDS IC
(IC101, pin 46) via the amplifier (Q152) as the comparison
signal.
The amplified signal from Q151 is applied to the PLL IC’s
1/21 divider section (IC201, pin 8), and is then applied to
the PLL section. The signal outputs from pin 2, and passes
through the loop filter (L221, C221, C222). The filtered
signal is applied to the one of the 6 VCOs circuits as follow.
RXPLL-B 1ST LO VCO TABLE
The oscillated signal is amplified at the buffer amplifier
(Q301), and passes through the high-pass (L331, C331–
C333) and low-pass (D341, L332, C334–C337) filters. The
signal is applied to the amplifier (Q302).
A portion of buffer amplified signal from Q301 is fed back to
the PLL IC’s 1/N (N=130–250) divider section (IC201, pin 6)
as the comparison signal via the buffer amplifier (Q303).
The amplified signal from Q302 is applied to another
amplifier (Q351), and is then amplified at the buffer
amplifier (Q352). The signal passes through the low-pass
filter (D441, L441, L442, C441–C446) and attenuator (R364
–R366), and is then output from J351 as the RX 1st LO
signal (64.585–124.555 MHz) to the RX-B circuit.
• 2ND LO CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(Q503) via the “40M” line, and is then applied to the DDS
IC (IC501, pin 88) as the system clock signal. The signals
which are output from pins 6–20 are applied to the D/A
convertor (R510–R533), and then passes through the low-
pass filter (L530–L532, C531–C536) to suppress more than
4.5 MHz signals. The filtered signal (4.0–4.0369735 MHz)
is applied to the amplifier (IC502, pin 2), and is then
applied to the DDS IC’s phase detector section (IC501, pin
47). The output signal from pin 56 passes through the loop
filter (D542, L541, C543, C543–C547, R548, R554), and is
then applied to the oscillator circuit (Q541) to oscillate the
64.591 MHz reference signal.
The 64.591 MHz signal is amplified at the buffer amplifier
(Q561), and is then applied to the hybrid divider.
A portion of 64.591 MHz signal passes through the
attenuator (R571, R572), and is then applied to the
amplifier (Q580). The amplified signal is applied to the
DDS IC’s quarter detector section (IC501, pin 80) as the
comparison signal.
The 64.591 MHz signal from the hybrid divider passes
through the attenuator (R587–R589), and is then applied to
the amplifier (Q591). The amplified signal passes through
the bandpass filter to suppress unwanted signals, and is
then applied to the RX 2nd mixer circuit (IC1501, IC1502)
as 2nd LO signal via the J561.
VCO No.
Parts No.
Oscillating frequencies
1
Q220
64.585–72.554999
MHz
2
Q230
72.555–79.554999
MHz
3
Q240
79.555–86.554999
MHz
4
Q250
86.555–94.554999
MHz
5
Q260
94.555–109.554999
MHz
6
Q270
109.555–124.555
MHz
