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• USING REFERENCE SIGNAL TO EXTERNAL
The oscillated signal is amplified at the buffer amplifier
(Q21), and is then applied to the amplifier (Q42). The
amplified signal is applied to the input-output switch (RL10)
via the low-pass filter (L43, L44, C46–C51), and is then
output from J71 after being passed through the 6 dB
attenuator (R71–R73).
• USING REFERENCE SIGNAL FROM EXTERNAL
The reference signal from the external equipment is applied
to the J71, and is then applied to the input-output switch
(RL10) via the 6 dB attenuator (R71–R73). The signal is
applied to the amplifier (Q61, Q62), and passes through
the bandpass filter (L61, L62, C66). The filtered signal is
applied to the reference signal switch (RL11), and is then
amplified at the buffer amplifier (Q70). The amplified signal
is applied to the RXPLL-A and RXPLL-B units via the J72
and J73, respectively.
3-3-3 RXPLL-A CIRCUIT (RXPLL-A UNIT)
The 10 MHz oscillated signal from the OSC unit is applied
to the amplifier (Q30) via the J10, and is then amplified at
the quadrupler (Q702) to produce 40 MHz reference signal.
The amplified signal passes through the bandpass filter
(L702, L703, C709–C713), and is then applied to the 1st
LO, maker, 2nd LO and 3rd LO circuits, respectively.
• 1ST LO CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(Q104) via the “40M” line, and is then applied to the DDS
IC (IC101, pin 88) as the system clock signal. The output
signals from pins 7
–20 pass through the D/A convertor
(R110–R133). The converted signal passes through the
ceramic filter (FI101) to pass the 10.5 MHz signal, and is
then applied to the amplifier (IC102, pin 2). The amplified
signal is applied to the DDS IC (IC101, pin 47) again, and
is then applied to the phase detector section of the DDS
IC. The signal which outputs from the DDS IC (IC101, pin
56) passes through the loop filter (L151, C152–C155), and
is then applied to the oscillator circuit (Q150). The circuit
oscillates 10.4122038–10.4963312 MHz signal.
The oscillated signal is applied to the amplifier (Q151), and
is then applied to the PLL IC (IC201).
A part of the oscillated signal is fed back to the DDS IC
(IC101, pin 46) via the amplifier (Q152) as the comparison
signal.
The amplified signal from Q151 is applied to the PLL IC’s
1/21 divider section (IC201, pin 8), and is then applied to
the PLL section. The signal outputs from pin 2, and passes
through the loop filter (L211, C221, C222). The filtered
signal is applied to the one of the 6 VCOs as follow.
RXPLL-A 1ST LO VCO TABLE
The oscillated signal is amplified at the buffer amplifier
(Q301), and passes through the high-pass (L331, C331–
C333) and low-pass (D341, L332, C334–C337) filters. The
filtered signal is applied to the amplifier (Q302).
A portion of buffer amplified signal from Q301 is fed back to
the PLL IC’s 1/N (N=130–250) divider section (IC201, pin 6)
via the buffer amplifier (Q303).
The amplified signal from Q302 is applied to another
amplifier (Q351), and is then amplified at the buffer
amplifier (Q352). The signal passes through the low-pass
(D441, L441, L442, C442–C446) and high-pass (L451, C447,
C451, C452) filters and attenuator (R364–R366), and is then
output from J351/J421 as the RX 1st LO signal (64.485–
124.455 MHz)/TX 1st LO signal (64.485–124.455 MHz) to
the TX/RX-A circuits respectively via the LO switches (D421,
D422).
• MARKER CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(Q104) via the “40M” line, and is then applied to the DDS
IC (IC101, pin 88) as the system clock signal.
The signal passes through the DDS IC’s 1/400 divider
section, and outputs from the IC (pin 49). The signal is
applied to the marker switch (IC602, pin 1), and is then
output from the IC (pin 4) as the 100 kHz marker signal.
• 2ND LO CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(IC503) via the “40M” line, and is then applied to the DDS
IC (IC501, pin 88) as the system clock signal. The signals
which are output from pins 6–20 are applied to the D/A
convertor (R510–R533), and then passes through the low-
pass filter (L530–L532, C531–C536) to suppress more than
4.5 MHz signals. The filtered signal (4.0–4.0306875 MHz)
is applied to the amplifier (IC502, pin 2), and is then
applied to the DDS IC’s phase detector section (IC501, pin
47). The output signal from pin 56 passes through the loop
filter (D542, L541, C543, C543–C547, R548, R554), and is
then applied to the oscillator circuit (Q541) to oscillate the
64 MHz reference signal.
The 64 MHz signal is applied to the buffer amplifier (Q561)
and the hybrid divider and then applied to the TX or RX
2nd LO circuits.
A portion of 64 MHz signal passes through the attenuator
(R571, R572), and is then applied to the amplifier (Q580).
The amplified signal is applied to the DDS IC’s quarter
detector section (IC501, pin 80) as the comparison signal.
(1) TX 2ND LO CIRCUIT
The signal from the hybrid divider passes through the
attenuator (R587–R589), and is then applied the amplifier
(Q591). The signal passes through the bandpass filter (L565,
L566, C573–C575) to suppress unwanted signals, and is
then applied to the TX 2nd mixer circuit (RX-A unit; D505)
via the J561.
VCO No.
Parts No.
Oscillating frequencies
1
Q220
64.485–72.454999
MHz
2
Q230
72.455–79.454999
MHz
3
Q240
79.455–86.454999
MHz
4
Q250
86.455–94.454999
MHz
5
Q260
94.455–109.454999
MHz
6
Q270
109.455–124.455
MHz
