User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006
Bus Interface Operation
Page 299 of 377
Misaligned data transfers when the 750GX is configured with a 32-bit data bus operate in the same way as
when configured with a 64-bit data bus, with the exception that only the DH[0–31] data bus is used. See
Table 8-7 on page 299 for an example of a 4-byte misaligned transfer starting at each possible byte address
within a double word.
Half word
0
1
0
000
A
A
—
—
x
x
x
x
0
1
0
010
—
—
A
A
x
x
x
x
0
1
0
100
A
A
—
—
x
x
x
x
0
1
0
110
—
—
A
A
x
x
x
x
Word
1
0
0
000
A
A
A
A
x
x
x
x
1
0
0
100
A
A
A
A
x
x
x
x
Double word
Second beat
0
0
0
000
A
A
A
A
x
x
x
x
0
0
0
000
A
A
A
A
x
x
x
x
Note:
A:
Byte lane used
—:
Byte lane not used
x:
Byte lane not used in 32-bit bus mode
Table 8-7. Misaligned 32-Bit Data-Bus Transfer (4-Byte Examples)
Transfer Size
(Four Bytes)
TSIZ[0–2]
A[29–31]
Data-Bus Byte Lanes
0
1
2
3
4
5
6
7
Aligned
1 0 0
0 0 0
A
A
A
A
x
x
x
x
Misaligned—first access
0 1 1
0 0 1
A
A
A
x
x
x
x
second access
0 0 1
1 0 0
A
—
—
—
x
x
x
x
Misaligned—first access
0 1 0
0 1 0
—
—
A
A
x
x
x
x
second access
0 1 0
1 0 0
A
A
—
x
x
x
x
x
Misaligned—first access
0 0 1
0 1 1
—
—
—
A
x
x
x
x
second access
0 1 1
1 0 0
A
A
A
—
x
x
x
x
Aligned
1 0 0
1 0 0
A
A
A
A
x
x
x
x
Misaligned—first access
0 1 1
1 0 1
—
A
A
A
x
x
x
x
second access
0 0 1
0 0 0
A
—
—
—
x
x
x
x
Misaligned—first access
0 1 0
1 1 0
—
—
A
A
x
x
x
x
second access
0 1 0
0 0 0
A
A
—
—
x
x
x
x
Misaligned—first access
0 0 1
1 1 1
—
—
—
A
x
x
x
x
second access
0 1 1
0 0 0
A
A
A
—
x
x
x
x
Note:
A:
Byte lane used
—:
Byte lane not used
x:
Byte lane not used in 32-bit bus mode
Table 8-6. Aligned Data Transfers (32-Bit Bus Mode)
(Page 2 of 2)
Transfer Size
TSIZ0
TSIZ1
TSIZ2
A[29–31]
Data-Bus Byte Lanes
0
1
2
3
4
5
6
7
