User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006
Bus Interface Operation
Page 305 of 377
Normal termination of a burst transfer occurs when TA is asserted for four bus clock cycles, as shown in
Figure 8-13. The bus clock cycles in which TA is asserted need not be consecutive, thus allowing pacing of
the data-transfer beats. For read bursts to terminate successfully, TEA and DRTRY must remain negated
during the transfer. For write bursts, TEA must remain negated for a successful transfer. DRTRY is ignored
during data writes.
Figure 8-12. Normal Single-Beat Write Termination
Figure 8-13. Normal Burst Transaction
0
1
2
3
TS
qual DBG
DBB
data
ta
drtry
AACK
1
2
3
4
5
6
7
TS
qual DBG
DBB
data
ta
drtry
