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User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

gx_06.fm.(1.2)
March 27, 2006 

 

Instruction Timing

Page 247 of 377

Store Word with Update 

Indexed

stwux

31

183

LSU

2:1

—

Store Word Indexed

stwx

31

151

LSU

2:1

—

TLB Invalidate Entry

tlbie

31

306

LSU

3:4

1

 Execution

Table 6-9. Load-and-Store Instructions 

 (Page 4 of 4)

Instruction

Mnemonic

Primary
Opcode

Extended

Opcode

Unit

Cycles

Serialization

1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for 

back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete 
the instruction to the cache, which stays busy keeping subsequent cache operations from executing.

2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space, 

throughput is at least 11 cycles.

3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n 

is the number of words accessed by the instruction. 

Summary of Contents for PowerPC 750GX

Page 1: ...IBM PowerPC 750GX and 750GL RISC Micro processor User s Manual Version 1 2 March 27 2006 Title Page...

Page 2: ...us uses where malfunction could result in death bodily injury or catastrophic property damage The information contained in this document does not affect or change IBM product specifications or warrant...

Page 3: ...nit SRU 32 1 2 3 Memory Management Units MMUs 32 1 2 4 On Chip Level 1 Instruction and Data Caches 33 1 2 5 On Chip Level 2 Cache Implementation 35 1 2 6 System Interface Bus Interface Unit BIU 35 1 2...

Page 4: ...r Support 83 2 2 3 2 Non IEEE Mode Nondenormalized Mode 83 2 2 3 3 Time Critical Floating Point Operation 84 2 2 3 4 Floating Point Storage Access Alignment 84 2 2 3 5 Optional Floating Point Graphics...

Page 5: ...2 3 4 1 2 Enabling and Disabling the Data Cache 132 3 4 1 3 Locking the Data Cache 132 3 4 1 4 Instruction Cache Flash Invalidation 133 3 4 1 5 Enabling and Disabling the Instruction Cache 133 3 4 1 6...

Page 6: ...x00700 170 4 5 8 Floating Point Unavailable Exception 0x00800 171 4 5 9 Decrementer Exception 0x00900 171 4 5 10 System Call Exception 0x00C00 171 4 5 11 Trace Exception 0x00D00 171 4 5 12 Floating Po...

Page 7: ...17 6 3 2 2 Cache Hit 217 6 3 2 3 Cache Miss 222 6 3 2 4 L2 Cache Access Timing Considerations 224 6 3 2 5 Instruction Dispatch and Completion Considerations 224 6 3 2 6 Rename Register Operation 224 6...

Page 8: ...rmination Signals 262 7 2 5 1 Address Acknowledge AACK Input 262 7 2 5 2 Address Retry ARTRY 263 7 2 6 Data Bus Arbitration Signals 264 7 2 6 1 Data Bus Grant DBG Input 264 7 2 6 2 Data Bus Write Only...

Page 9: ...Bus Signal Clocking 282 8 1 4 Optional 32 Bit Data Bus Mode 282 8 1 5 Direct Store Accesses 283 8 2 Memory Access Protocol 284 8 2 1 Arbitration Signals 285 8 2 2 Miss under Miss 286 8 2 2 1 Miss unde...

Page 10: ...thods 332 9 8 1 L2CR Support for L2 Cache Testing 332 9 8 2 L2 Cache Testing 333 9 9 L2 Cache Timing 333 10 Power and Thermal Management 335 10 1 Dynamic Power Management 335 10 2 Programmable Power M...

Page 11: ...truction Address Register SIA 355 11 2 1 8 User Sampled Instruction Address Register USIA 355 11 3 Event Counting 355 11 4 Event Selection 356 11 5 Notes 356 11 6 Debug Support 357 11 6 1 Overview 357...

Page 12: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Page 12 of 377 750gx_umTOC fm 1 2 March 27 2006...

Page 13: ...e 5 4 Address Translation Types 187 Figure 5 5 General Flow of Address Translation Real Addressing Mode and Block 189 Figure 5 6 General Flow of Page and Direct Store Interface Address Translation 191...

Page 14: ...re 8 17 Fastest Single Beat Reads 310 Figure 8 18 Fastest Single Beat Writes 311 Figure 8 19 Single Beat Reads Showing Data Delay Controls 312 Figure 8 20 Single Beat Writes Showing Data Delay Control...

Page 15: ...96 Table 2 13 Floating Point Multiply Add Instructions 96 Table 2 14 Floating Point Rounding and Conversion Instructions 97 Table 2 15 Floating Point Compare Instructions 97 Table 2 16 Floating Point...

Page 16: ...nse to Snooped Bus Transactions 143 Table 3 6 Address Transfer Attribute Summary 146 Table 3 7 MEI State Transitions 147 Table 4 1 PowerPC 750GX Microprocessor Exception Classifications 152 Table 4 2...

Page 17: ...ry of Mode Select Signals 274 Table 7 7 Bus Voltage Selection Settings 275 Table 7 8 IEEE Interface Pin Descriptions 275 Table 8 1 Transfer Size Signal Encodings 294 Table 8 2 Burst Ordering 64 Bit Bu...

Page 18: ...s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor List of Tables Page 18 of 377 750gx_umLOT fm 1 2 March 27 2006 Table 11 7 HID2 Checkstop Control Bits 362 Table 11 8 L2CR Checkstop Control Bit...

Page 19: ...a New Family of RISC Proces sors Second Edition San Francisco CA Morgan Kaufmann 1994 McClanahan Kip PowerPC Programming for Intel Programmers Foster City CA Hungry Minds 1995 Shanley Tom PowerPC Syst...

Page 20: ...ister GPR rD Instruction syntax used to identify a destination GPR frA frB frC Instruction syntax used to identify a source Floating Point Register FPR frD Instruction syntax used to identify a destin...

Page 21: ...l Data storage interrupt DSI DSI exception Extended mnemonics Simplified mnemonics Fixed point unit FXU Integer unit IU Instruction storage interrupt ISI ISI exception Interrupt Exception Privileged m...

Page 22: ...d other devices can access external memory Implementations that conform to the PowerPC VEA also conform to the PowerPC UISA but might not necessarily adhere to the OEA PowerPC operating environment ar...

Page 23: ...anch processing unit BPU System register unit SRU Load store unit LSU Two integer units IUs IU1 executes all integer instructions IU2 executes all integer instructions except multiply and divide instr...

Page 24: ...ate cache coherency protocol MEI supports the modi fied exclusive and invalid states a compatible subset of the MESI modified exclusive shared invalid 4 state protocol and it operates coherently in sy...

Page 25: ...the BTIC it is fetched into the instruction queue a cycle sooner than it can be Figure 1 1 750GX Microprocessor Block Diagram Ifetch Branch Processing BTIC 64 Entries x FPSCR FPSCR CTR LR BHT Data MM...

Page 26: ...ical operations Hardware support for denormalized numbers Hardware support for divide 2 entry reservation station Thirty two 64 bit Floating Point Registers FPRs for single and double precision operat...

Page 27: ...nstruction cache one outstanding miss Nonblocking data cache four outstanding misses No snooping of instruction cache Parity for L1 tags and caches Integrated L2 cache 1 MB on chip ECC SRAMs On chip 4...

Page 28: ...forced 3 state cache coherency protocol MEI for data cache Load store with reservation instruction pair for atomic memory references semaphores and other multiprocessor operations Power and thermal ma...

Page 29: ...The instruction fetcher continuously attempts to load as many instructions as there were vacancies created in the IQ in the previous clock cycle All instructions except branches are dispatched to thei...

Page 30: ...fi instruction execution or when an exception is taken The BPU contains an adder to compute branch target addresses and three user control registers the Link Register LR the Count Register CTR and the...

Page 31: ...require full 32 32 bit multiplication Multiply and divide instructions spend several cycles in the execution stage before the results are written to the output rename buffer 1 2 2 2 Floating Point Uni...

Page 32: ...and a miss queue A load that misses in the dcache advances from Eib0 to the miss queue where only necessary state for instruction completion like the instruction ID and register rename ID are stored...

Page 33: ...virtual address This 52 bit virtual address is translated into a physical address by doing a lookup in the TLB If the lookup is successful a physical address is formed by using 16 low order bits from...

Page 34: ...e invalidated all at once or on a per cache block basis The data cache can be disabled and invalidated by clearing the data cache enable bit HID0 DCE and setting the data cache flash invalidate bit HI...

Page 35: ...ly oper ates in write back mode and supports cache coherency through snooping The access interface to the L2 is 64 bits for writes and requires four cycles to write a single cache block The access int...

Page 36: ...nstructions do not necessarily complete in the order they begin This maximizes the efficiency of the bus without sacrificing data coherency The 750GX allows read operations to go ahead of store operat...

Page 37: ...ess start This signal indicates that a bus master has begun a transaction on the address bus Address transfer These signals include the address bus and are used to transfer the address Transfer attrib...

Page 38: ...they are low 1 2 8 Signal Configuration Figure 1 4 shows the 750GX s logical pin configuration The signals are grouped by function Interrupt These signals include the interrupt signal checkstop signal...

Page 39: ...or Signal Groups BR BG ABB TS AP 0 3 GBL TSIZ 0 2 AACK ARTY SYSCLK DBG DBWO DBB D 0 63 DP 0 7 TA DRTRY TEA INT RSRVR JTAG COP FACTORY TEST 1 1 1 1 1 5 3 4 TBST WT PLL_CFG 0 4 TT 0 4 5 5 TBEN 1 CLK_OUT...

Page 40: ...ure technological gains The remainder of this chapter describes the PowerPC Architecture in general and specific details about the implementation of 750GX as a low power 32 bit member of the PowerPC p...

Page 41: ...ower and Thermal Management on page 335 Thermal management Section 1 11 Thermal Management on page 55 describes how the thermal management unit and its associated registers THRM1 THRM4 and exception p...

Page 42: ...ruction operands to access the register For more information see Chapter 2 Programming Model on page 57 The following tables summarize the PowerPC registers implemented in 750GX and describe registers...

Page 43: ...address after branch and link instructions BATs Supervisor The architecture defines eight Block Address Translation Registers BATs each imple mented as a pair of 32 bit SPRs In the 750GX the BAT faci...

Page 44: ...egister ICTC has bits for controlling the interval at which instructions are fetched into the instruction buffer in the instruction unit This helps control the 750GX s overall junction temperature L2C...

Page 45: ...tructions Floating point multiply add instructions Floating point rounding and conversion instructions Floating point compare instructions Floating point status and control instructions Load store ins...

Page 46: ...GPRs It also provides for single and double precision loads and stores between memory and a set of 32 Floating Point Registers FPRs Computational instructions do not access memory To use a memory oper...

Page 47: ...ache Operation on page 121 A detailed description of the L2 cache is provided in Chapter 9 L2 Cache on page 323 1 6 1 PowerPC Cache Model The PowerPC Architecture does not define hardware aspects of c...

Page 48: ...ere fore although a particular implementation might recognize exception conditions out of order they are handled in program order When an instruction caused exception is recognized any unexecuted inst...

Page 49: ...xception handler When an exception is taken due to a trap or system call instruction execution resumes at an address provided by the handler Synchronous imprecise The PowerPC Architecture defines two...

Page 50: ...ching inhibited or the cache is disabled Program 00700 As defined by the PowerPC Architecture Floating point unavailable 00800 As defined by the PowerPC Architecture Decrementer 00900 As defined by th...

Page 51: ...ional cycles incurred The 750GX MMU provides independent 8 entry BAT arrays for instructions and data that maintain address translations for blocks of memory These entries define blocks that can vary...

Page 52: ...single cycle allowing multiple instructions to execute in parallel The 750GX has six independent execution units two for integer instructions and one each for floating point instructions branch instru...

Page 53: ...s and determining which instructions can be dispatched To qualify for dispatch a reser vation station a rename buffer and a position in the completion queue all must be available A branch instruction...

Page 54: ...signal an exception The completion unit retires instructions from the bottom two positions of the completion queue in program order This maintains the correct architectural machine state and transfer...

Page 55: ...temperature with an external thermal sensor the 750GX s on chip thermal sensor and logic tightly couple the thermal manage ment implementation The TAU consists of a thermal sensor digital to analog co...

Page 56: ...on page 335 provides information about power saving and thermal management modes for the 750GX 1 12 Performance Monitor The 750GX incorporates a performance monitor facility that system designers can...

Page 57: ...nvironments Manual Registers are defined at all three levels of the PowerPC Architecture user instruction set architecture UISA virtual environment architecture VEA and operating environment architect...

Page 58: ...1 Instruction Cache Throttling Control Register1 USER MODEL VEA TBL TBR 268 Time Base Facility For Reading CTR GPR0 GPR1 GPR31 TBU TBR 269 IBAT0U IBAT0L IBAT1U IBAT1L IBAT2U IBAT2L IBAT3U IBAT3L SPR 5...

Page 59: ...he Programming Environments Manual Floating Point Status and Control Register FPSCR The FPSCR contains all floating point excep tion signal bits exception summary bits exception enable bits and roundi...

Page 60: ...s the 750GX implements that are not required by the PowerPC Architecture Note Setting MSR EE masks not only the architecture defined external interrupt and decre menter exceptions but also the 750GX s...

Page 61: ...ster are interpreted differently depending on the value of bit 0 See Segment Regis ters in Chapter 2 PowerPC Register Set of the PowerPC Microprocessor Family The Programming Environments Manual for m...

Page 62: ...at a speed that is one fourth the speed of the bus clock Data Address Breakpoint Register DABR This optional register is used to cause a breakpoint exception if a specified data address is encountered...

Page 63: ...SIA provides user level read access to the SIA The 750GX does not implement the Sampled Data Address Register SDA or the user level read only USDA registers However for compatibility with processors t...

Page 64: ...ve address stored in the IABR If the word specified in the IABR is fetched the instruction breakpoint handler is invoked The instruction that triggers the breakpoint does not execute before the handle...

Page 65: ...and thus should be left unconnected If all parity generation is disabled all parity checking should also be disabled and parity signals need not be connected 2 EBA1 Enable disable 60x bus address pari...

Page 66: ...from a soft reset 0 A hard reset has occurred if software previously set this bit 1 A hard reset has not occurred If software sets this bit after a hard reset when a reset occurs and this bit remains...

Page 67: ...erations Setting ICFI clears all the valid bits of the blocks and the pseudo least recently used PLRU bits to point to way L0 of each set Once the L1 flash invalidate bits are set through an mtspr ope...

Page 68: ...routine and should be cleared when the series of instructions completes 26 BTIC Branch target instruction cache enable used to enable use of the 64 entry branch instruction cache 0 The BTIC is disabl...

Page 69: ...onal Branch Control in Chapter 4 of the Pow erPC Microprocessor Family The Programming Environments Manual 1 Allows the use of the 512 entry branch history table BHT The BHT is disabled at power on re...

Page 70: ...cessor clock source 8 ECLK Set to 1 to enable the CLKOUT pin 9 11 Reserved Select the internal clock to be output on the CLKOUT pin with the following decode 000 Factory use only 001 PLL0 core clock f...

Page 71: ...9 30 31 Bits Field Name Description Notes 0 2 Reserved Reserved 1 3 STMUMD Disable store miss under miss processing changes the allowed outstanding store misses from two to one 4 19 Reserved Reserved...

Page 72: ...8 29 30 31 Bits Field Name Description 0 DIS Disables counting unconditionally 0 The values of the PMCn counters can be changed by hardware 1 The values of the PMCn counters cannot be changed by hardw...

Page 73: ...signaling when the bit identified in RTCSELECT transitions from off to on 0 Do not allow interrupt signal if chosen bit transitions 1 Signal interrupt if chosen bit transitions Software is responsibl...

Page 74: ...interrupt signal condition can occur with MSR EE cleared but the exception is not taken until EE is set Setting MMCR0 DISCOUNT forces counters to stop counting when a counter interrupt occurs Software...

Page 75: ...struction Address Register SIA The Sampled Instruction Address Register SIA is a supervisor level register that contains the effective address of an instruction executing at or around the time that th...

Page 76: ...y user level software USIA can be accessed with the mfspr instructions using SPR 939 Sampled Data Address Register SDA and User Sampled Data Address Register USDA The 750GX does not implement the Samp...

Page 77: ...configurations are unchanged Instruction cache throttling is enabled by setting ICTC E and writing the instruction forwarding interval into ICTC FI Enabling disabling and changing the instruction for...

Page 78: ...its Field Name Description 0 TIN Thermal management interrupt bit Read only This bit is set if the thermal sensor output crosses the threshold specified in the SPR The state of this bit is valid only...

Page 79: ...is not valid 0 1 0 x 1 The junction temperature is less than the threshold and as a result the thermal man agement interrupt is not generated for TIE 1 1 1 0 x 1 The junction temperature is greater th...

Page 80: ...threshold mode TOFFSET should be subtracted from the desired temperature before setting the THRMn THRESHOLD field In junction temperature determination mode TOFFSET must be added to the final thresho...

Page 81: ...han the default copy back mode so all writes to the L2 cache also write through to the 60x bus 13 TS L2 test support Setting TS causes cache block pushes from the L1 data cache that result from dcbf a...

Page 82: ...permitted as memory oper ands quadwords are shown because quadword alignment is desirable for certain memory operands The concept of alignment is also applied more generally to data in memory For exa...

Page 83: ...s NaNs follow the conventions described in that section Although the double precision format specifies an 11 bit exponent exponent arithmetic uses two additional bit positions to avoid potential trans...

Page 84: ...Point as Integer Word Indexed stfiwx Floating Select fsel fres and frsqrte For Floating Reciprocal Estimate Single A Form fres the esti mate is 12 bits of precision For Floating Reciprocal Square roo...

Page 85: ...IEEE Mode NI 0 Non IEEE Mode NI 1 Single Denormalized Return single precision denormalized number with trail ing zeros Return zero Single Normalized infinity zero Return the result Return the result...

Page 86: ...set of simplified mnemonics and symbols is provided for some of the frequently used instructions see Appendix F Simplified Mnemonics in the PowerPC Micro processor Family The Programming Environments...

Page 87: ...ved fields the results on execution can be said to be boundedly undefined If a user level program executes the incorrectly coded instruction the resulting undefined results are bounded in that a spuri...

Page 88: ...d opcodes for instructions defined only for 64 bit implemen tations are illegal in 32 bit implementations and vice versa The following primary opcodes have unused extended opcodes 17 19 31 59 63 prima...

Page 89: ...es and Instruction Set Summary of the PowerPC Micropro cessor Family The Programming Environments Manual 2 3 2 1 Memory Addressing A program references memory using the effective logical address compu...

Page 90: ...he synchronization described in this section refers to the state of the processor that is performing the synchronization Context Synchronization The System Call sc and Return from Interrupt rfi instru...

Page 91: ...ent Register Indirect mtsrin Return from Exception rfi TLB Invalidate Entry tlbie TLB Synchronize tlbsync Note that the privilege level of the mfspr and mtspr instructions depends on the SPR encoding...

Page 92: ...ibes the integer instructions which consist of Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate and shift instructions Integer instructions use...

Page 93: ...signed immediate value UIMM operand the sign extended value of the signed immediate value SIMM operand or the contents of register rB The comparison is signed for the cmpi and cmp instructions and uns...

Page 94: ...its of a register left justifying or right justifying an arbi trary field and simple rotates and shifts Integer rotate instructions rotate the contents of a register The result of the rotation is eith...

Page 95: ...following Floating point arithmetic instructions Floating point multiply add instructions Floating point rounding and conversion instructions Floating point compare instructions Floating point status...

Page 96: ...dd frD frA frB Floating Add Single fadds fadds frD frA frB Floating Subtract Double Precision fsub fsub frD frA frB Floating Subtract Single fsubs fsubs frD frA frB Floating Multiply Double Precision...

Page 97: ...on ensures that all floating point instructions previously initi ated by the given processor appear to have completed before the FPSCR instruction is initiated and that no subsequent floating point in...

Page 98: ...provides hardware support for misaligned memory accesses It performs those accesses within a single cycle if the operand lies within a double word boundary Misaligned memory accesses that cross a dou...

Page 99: ...Coherency in the PowerPC Microprocessor Family The Programming Environments Manual Because the 750GX does not broadcast the M bit for instruction fetches external caches are subject to coherency para...

Page 100: ...f these preferred forms affect instruction performance on the 750GX The PowerPC Architecture defines the load word and reserve indexed lwarx and the store word condi tional indexed stwcx instructions...

Page 101: ...or to cache inhibited stores to nonguarded space if the stores are 4 bytes and they are word aligned These stores are combined in the load store unit LSU to form a double word that is sent out on the...

Page 102: ...tructions can have operands that require memory accesses that cross a 4 KB page boundary As a result these instructions might be interrupted by a DSI exception associated with the address translation...

Page 103: ...er than a word aligned string operation Implementation Notes The following describes the 750GX implementation of load store string instructions For load store string operations the hardware does not c...

Page 104: ...3 summarizes the single precision and double precision floating point load instructions Floating Point Store Instructions This section describes floating point store instructions There are three basic...

Page 105: ...g Point Single stfs frS d rA Store Floating Point Single Indexed stfsx frS rB Store Floating Point Single with Update stfsu frS d rA Store Floating Point Single with Update Indexed stfsux frS rB Store...

Page 106: ...ditionally based on the value of bits in the CR When the processor encounters one of these instructions it scans the execution pipelines to determine whether an instruction in progress can affect the...

Page 107: ...uctions and the Move Condition Register Field mcrf instruction are also defined as flow control instructions Table 2 28 shows these instructions Note If the LR update option is enabled for any of thes...

Page 108: ...ting this instruction causes the system call exception handler to be evoked For more information see Section 4 5 10 on page 171 2 3 4 6 Processor Control Instructions UISA Processor control instructio...

Page 109: ...6 10000 11000 Supervisor OEA Both DBAT1L 539 10000 11011 Supervisor OEA Both DBAT1U 538 10000 11010 Supervisor OEA Both DBAT2L 541 11110 11101 Supervisor OEA Both DBAT2U 540 11110 11100 Supervisor OEA...

Page 110: ...th LR 8 00000 01000 User UISA Both PVR 287 01000 11111 Supervisor OEA mfspr SDR1 25 00000 11001 Supervisor OEA Both SPRG0 272 01000 10000 Supervisor OEA Both SPRG1 273 01000 10001 Supervisor OEA Both...

Page 111: ...compared with actual instruction coding For mtspr and mfspr instructions the SPR number coded in assembly language does not appear directly as a 10 bit binary number in the instruction The number cod...

Page 112: ...erved2 921 924 Supervisor SIA 955 11101 11011 Supervisor Both THRM1 1020 11111 11100 Supervisor Both THRM2 1021 11111 11101 Supervisor Both THRM3 1022 11111 11110 Supervisor Both THRM4 920 11100 11000...

Page 113: ...rol Instructions VEA In addition to the Move to Condition Register instructions specified by the UISA the VEA defines the mftb instruction user level instruction for reading the contents of the Time B...

Page 114: ...gh the use of the Move from Time Base mftb and the Move from Time Base Upper mftbu instructions As a 32 bit PowerPC imple mentation the 750GX can access TBU and TBL only separately whereas 64 bit impl...

Page 115: ...adcasts an icbi Of the broadcast cache operations the 750GX snoops only dcbz regardless of the HID0 ABE setting Any bus activity caused by other cache instructions results directly from performing the...

Page 116: ...t Data Cache Block Touch for Store1 dcbtst rA rB This instruction behaves like dcbt Data Cache Block Set to Zero dcbz rA rB The EA is computed translated and checked for protection violations For cach...

Page 117: ...and the cache entry is invalidated For cache hits with the tag marked exclusive unmodified E the entry is invalidated For cache misses no further action is taken A dcbf is not broadcast unless HID0 A...

Page 118: ...for accessing the MSR The OEA defines encodings of mtspr and mfspr to provide access to supervisor level registers The instruc tions are listed in Table 2 42 Encodings for the architecture defined SPR...

Page 119: ...Buffers in Chapter 2 PowerPC Register Set of the PowerPC Microprocessor Family The Programming Environments Manual for serializa tion requirements and other recommended precautions to observe when ma...

Page 120: ...presence and exact semantics of the TLB management instructions are implementation dependent To minimize compatibility problems system software should incorporate uses of these instructions into subr...

Page 121: ...ressed The physical real address tag is stored in the cache directory Both the instruction and data caches have 32 byte cache blocks A cache block is the block of memory that a coherency state describ...

Page 122: ...cache is supported by two cache block reload write back buffers This allows a cache block to be loaded or unloaded from the cache in a single cycle See Figure 9 1 on page 327 The data cache supplies...

Page 123: ...n a block The two state bits implement a 3 state MEI protocol a coherent subset of the standard 4 state modified exclusive shared invalid MESI protocol The MEI protocol is described in Section 3 3 2 o...

Page 124: ...instruction cache differs from the data cache in that it does not implement MEI cache coherency protocol and a single state bit is implemented that indicates only whether a cache block is valid or inv...

Page 125: ...herency in this section applies to the 750GX s data cache only The instruction cache is not snooped Instruction cache coherency must be maintained by soft ware However the 750GX does support a fast in...

Page 126: ...f coherent memory support is desired Careless specification of these bits might create situations that present coherency paradoxes to the processor In particular this can happen when the state of thes...

Page 127: ...a snooped transaction is a caching inhibited read1 in which case the 750GX does not invalidate the snooped cache block If the cache block is modified the block is written back to memory and the cache...

Page 128: ...n the snoop coincides with a tag write for example validation after a cache block load In these situations the snoop is retried and must rearbitrate before the lookup is possible Occasionally cache sn...

Page 129: ...n is not marked global Also because cache block castouts and snoop pushes do not require snooping the GBL signal is not asserted for these operations When the 750GX detects a qualified snoop condition...

Page 130: ...memory request into the processor s memory queue but such operations are considered an extension to the state of the cache with respect to snooping bus operations Caching inhibited WIMG x1xx loads cac...

Page 131: ...is locked and the access misses then the lwarx instruction appears on the bus as a single beat load All bus operations that are a direct result of either an lwarx instruction or an stwcx instruction...

Page 132: ...ccesses is controlled by MSR DR The setting of the DCE bit must be preceded by a synchronization sync instruction to prevent the cache from being enabled or disabled in the middle of a data access In...

Page 133: ...sses is controlled by MSR IR The setting of the ICE bit must be preceded by an instruction sync isync instruction to prevent the cache from being enabled or disabled in the middle of an instruction fe...

Page 134: ...essed byte with respect to address translation and protection If the block containing the byte addressed by the EA is in the data cache all bytes are cleared and the tag is marked as modified M If the...

Page 135: ...n the PowerPC Architecture This instruction is treated as a load with respect to address translation and memory protection If the address hits in the cache and the block is in the modified M state the...

Page 136: ...w block needs to be placed in the cache When the data to be replaced is in the modified M state that data is written into a castout buffer while the missed data is being accessed on the bus When the l...

Page 137: ...lace L1 Replace L2 Replace L3 Replace L4 Replace L5 Replace L6 Replace L7 B0 0 B4 0 B1 0 B1 1 B2 1 B2 0 B0 1 B3 0 B3 1 B4 1 B5 0 B5 1 B6 0 B6 1 Allocate L0 L0 invalid Allocate L2 L2 invalid Allocate L...

Page 138: ...of dcbi instructions or by setting HID0 DCFI Any modified entries in the data cache can be copied back to memory flushed by using the dcbf instruction or by executing a series of 12 uniquely addresse...

Page 139: ...the requesting unit thus minimizing stalls due to cache fill latency A cache block is filled after a read miss or write miss read with intent to modify occurs in the cache The cache block that corres...

Page 140: ...es to both the data and instruc tion cache 3 6 1 Read Operations and the MEI Protocol The MEI coherency protocol affects how the 750GX data cache performs read operations on the 60x bus All reads exce...

Page 141: ...ns initiated by cache control instructions Note that the information in this table assumes that the WIM bits are set to 001 that is the cache is operating in write back mode caching is enabled and coh...

Page 142: ...struction cache for coherency The memory queues are snooped for pipeline collisions and memory coherency collisions A pipeline collision is detected when another bus master addresses any portion of a...

Page 143: ...r dcbi instruction is executed If the addressed cache block is in the exclusive E state the cache block is placed in the invalid I state If the addressed cache block is in the modified M state the 750...

Page 144: ...te If the address misses in the cache no action is taken Read with intent to modify RWITM 01110 A RWITM operation is issued to acquire exclusive use of a memory location for the purpose of modifying i...

Page 145: ...r External Control In Word Indexed eciwx and ecowx bus transactions independent of the address translation The GBL signal reflects the memory coherency requirements the complement of the M bit of the...

Page 146: ...he disabled PA 0 31 A 1 0 1 0 1 S S S M 0 I Single beat write caching inhibited write through or cache disabled PA 0 31 0 0 0 1 0 1 S S S M W I Special instructions dcbz address only PA 0 28 0b000 0 1...

Page 147: ...I Same Cast out of modified block if neces sary Write with kill Pass RWITM to memory queue RWITM Store T 0 Write No 00x E M M Write data to cache Store stwcx T 0 Write No 10x I Same Pass single beat...

Page 148: ...k touch No x1x M I Push block to write queue Write with kill dcbt Data cache block touch No x0x I Same Cast out of modified block as required Write with kill Pass 4 beat read to memory queue Read dcbt...

Page 149: ...n Page 149 of 377 tlbie TLB invalidate No xxx x x Pass TLBI No action sync Synchroniza tion No xxx x x Pass sync No action Table 3 7 MEI State Transitions Page 3 of 3 Operation Cache Operation Bus Syn...

Page 150: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Instruction Cache and Data Cache Operation Page 150 of 377 gx_03 fm 1 2 March 27 2006...

Page 151: ...n stream including any that have not yet entered the execute state are required to complete before the exception is taken For example if a single instruction encounters multiple exception conditions t...

Page 152: ...or Family The Programming Environments Manual Exceptions implemented in 750GX and conditions that cause them are listed in Table 4 2 Table 4 1 PowerPC 750GX Microprocessor Exception Classifications Sy...

Page 153: ...tion completion is defined as updating all architectural registers associated with that instruction and then removing that instruction from the completion buffer Program 00700 As defined by the PowerP...

Page 154: ...instruction processing at which they generate an exception Instruction fetch Instruction storage interrupt ISI exceptions Once this type of exception is detected dispatching stops and the current inst...

Page 155: ...ram exception due to floating point enabled exception 5 DSI Data storage exception due to eciwx ecowx with the enable bit of the External Access Reg ister cleared EAR E 0 bit 11 of DSISR 6 Alignment A...

Page 156: ...Status Save Restore Register 1 SRR1 to save the contents of the Machine State Register MSR for the current context 4 3 1 Machine Status Save Restore Register 0 SRR0 When an exception occurs the addre...

Page 157: ...it A data parity error on the 60x bus is indicated by the DP bit The MCpin bit indicates that the machine check pin was activated The transfer error acknowledge TEA bit indicates the machine check was...

Page 158: ...nter excep tion conditions 1 The processor is enabled to take an external interrupt or the decrementer excep tion 17 PR Privilege level 0 The processor can execute both user and supervisor level instr...

Page 159: ...address translation is disabled 1 Instruction address translation is enabled For more information see Chapter 5 Memory Management on page 179 27 DR Data address translation 0 Data address translation...

Page 160: ...dled and by confirming that the exception is enabled for the exception condition the processor does the following 1 SRR0 is loaded with an instruction address that depends on the type of exception Nor...

Page 161: ...he GRPs that was saved This GPR now points to the save area in mem ory Move the GPRs SRR0 SRR1 SPRG1 3 and other registers to be used by the exception routine into the stack saved area Update SPGR0 to...

Page 162: ...that an lwarx instruction in an old process is not paired with an stwcx instruction in a new one The operating system should set MSR RI as described in Section 4 3 6 Setting MSR RI 4 5 Exception Defin...

Page 163: ...t and tell whether a subsequent reset is a hard or soft reset by examining whether this bit is still set The first bus operation following the negation of HRESET or the assertion of SRESET will be a s...

Page 164: ...Attempts to use SRESET during a hard reset sequence or while the Joint Test Action Group JTAG logic is non idle cause unpredictable results see Section 7 2 10 2 Soft Reset SRESET Input on page 272 for...

Page 165: ...ion It is always nonrecover able Table 4 7 on page 166 shows the state of the machine just before it fetches the first instruction of the system reset handler after a hard reset In Table 4 7 the term...

Page 166: ...00000000 GPRs Unknown HID0 00000000 HID1 00000000 IABR All zeros break point disabled ICTC 00000000 L2CR 00000000 LR 00000000 MMCRn 00000000 MSR 00000040 only IP set PMCn Unknown PVR See the PowerPC...

Page 167: ...Bits Bits Field Name Description 0 EMCP Enable MCP The primary purpose of this bit is to mask out further machine check excep tions caused by assertion of MCP similar to how MSR EE can mask external i...

Page 168: ...SR ME 1 Machine check exceptions are enabled when MSR ME 1 When a machine check exception is taken registers are updated as shown in Table 4 9 The machine check exception is usually unrecoverable in t...

Page 169: ...ements the data address breakpoint facility which is defined as optional in the PowerPC Architecture and is supported by the optional Data Address Breakpoint Register DABR Although the archi tecture d...

Page 170: ...rPC Architecture For more information see Section 4 5 3 DSI Exception 0x00300 on page 169 4 5 7 Program Exception 0x00700 The 750GX implements the program exception as it is defined by the PowerPC Arc...

Page 171: ...Register settings for this exception are described in Chapter 6 Exceptions in the PowerPC Microprocessor Family The Program ming Environments Manual When a decrementer exception is taken instruction...

Page 172: ...are used to enable various performance moni tor interrupt functions UMMCR0 UMMCR1 provide user level read access to these registers The Sampled Instruction Address Register SIA contains the effective...

Page 173: ...akpoint is enabled by the mtspr instruction to the IABR immediately preceding it The 750GX also cannot block a breakpoint response on the context synchronizing instruction if the breakpoint was disabl...

Page 174: ...crosses a threshold programmed in either THRM1 or THRM2 The exception is enabled by the thermal management interrupt enable TIE bit of either THRM1 or THRM2 and can be masked by setting MSR EE Table...

Page 175: ...it Bit 30 is a store enable Bit 31 is a load enable The DABR is enabled by setting either the data store enable DW or data read enabled DR bit The format of the DABR register is shown in Section 4 5 1...

Page 176: ...ion Handling Table 4 14 describes how the 750GX handles exceptions up to the point of signaling the appropriate excep tion to occur Note that a recoverable state is reached in the 750GX if the complet...

Page 177: ...f the machine If completing any of the instructions in this stream causes an exception that exception is taken and the instruc tion fetch exception is forgotten Otherwise once the machine is empty and...

Page 178: ...User s Manual IBM PowerPC 750GX and GL RISC Microprocessor Exceptions Page 178 of 377 gx_04 fm 1 2 March 27 2006...

Page 179: ...ent registers on 32 bit implementations such as the 750GX In addition two translation lookaside buffers TLBs are implemented on the 750GX to keep recently used page address translations on chip Althou...

Page 180: ...nd the MMU attempts to fetch the page table entry PTE which contains the physical address from the appropriate TLB on chip If the translation is not found in a TLB that is a TLB miss occurs the hardwa...

Page 181: ...and changed C bits in the translation table In the event of a TLB miss the hardware attempts to load the TLB based on the results of a translation table search operation Figure 5 2 PowerPC 750GX Micr...

Page 182: ...e operating system Section 4 3 Exception Processing on page 156 describes the MSR which controls some of the critical functionality of the MMUs The figures show how address bits A 20 26 index into the...

Page 183: ...Optional Instruction Accesses Data Accesses EA 0 19 Segment Registers On Chip TLBs Optional Page Table Search Logic Optional SDR1 SPR 25 PA 0 14 X PA 0 19 PA 15 19 PA 0 31 A 20 31 IBAT0U IBAT0L IBAT7U...

Page 184: ...Microprocessor IMMU Block Diagram BPU ITLB IBAT Array 0 63 127 Tag PA 0 19 Instruction Cache Select Instruction Cache Compare Compare Compare 0 7 Instruction Unit A 20 31 Hit Miss Segment Registers 0...

Page 185: ...750GX Microprocessor DMMU Block Diagram DTLB DBAT Array 0 63 127 Tag PA 0 19 Data Cache Select Data Cache Compare Compare Compare 0 7 A 20 31 Hit Miss Segment Registers 0 15 DBAT0U DBAT0L DBAT7U DBAT7...

Page 186: ...Section 4 5 4 ISI Exception 0x00400 on page 169 For memory accesses translated by a segment descriptor the interim virtual address is generated using the information in the segment descriptor Page add...

Page 187: ...resses to physical addresses the MMUs provide access protec tion of supervisor areas from user access and can designate areas of memory as read only as well as no execute or guarded Table 5 2 on page...

Page 188: ...ch areas of memory to write back to disk when new pages must be allo cated in main memory While these bits are initially programmed by the operating system into the page table the architecture specifi...

Page 189: ...sing mode block address translation or the segment descriptor to select page address translation Note If the BAT array search results in a hit then the access is qualified with the appropriate protect...

Page 190: ...iptor for an access is contained in one of the 16 on chip Segment Registers Effective address bits EA 0 3 select one of the 16 Segment Registers Note The 750GX does not implement the direct store inte...

Page 191: ...instruction accesses causes ISI exception Load TLB Entry See Figure 5 8 on page 203 See Figure 5 9 on page 205 Otherwise Check T Bit in Segment Descriptor Use EA 0 3 to Select One of 16 On Chip Segmen...

Page 192: ...complete any memory access the effective address must be translated to a physical address As speci fied by the architecture an MMU exception condition occurs if this translation fails for one of the...

Page 193: ...or a complete description of the SRR1 and DSISR bit settings for these exceptions Instruction fetch from direct store seg ment Attempt to fetch instruction when SR T 1 ISI exception SRR1 3 1 Data acce...

Page 194: ...e impact of migrating across the family of implementations Table 5 5 summarizes the 750GX s instructions that specifically control the MMU For more detailed informa tion about the instructions see Cha...

Page 195: ...ously invalidating four TLB entries The index corresponds to bits 14 19 of the EA Software must ensure that instruction fetches or memory references to the virtual pages specified by the tlbie instruc...

Page 196: ...Always reset to zero during the reset Interrupt Service Routine ISR After zeroing all BATs set them in order to the desired values A hard reset HRESET disorders the BATs A soft reset SRESET does not 5...

Page 197: ...sabled real addressing mode If these update accesses hit in the data cache they are not seen on the external bus If they miss in the data cache they are performed as typical cache line fill accesses o...

Page 198: ...e the R bit to be set they never cause the C bit to be set 5 4 1 3 Scenarios for Referenced and Changed Bit Recording This section provides a summary of the model defined by the OEA that is used by Po...

Page 199: ...e defines a single set of Segment Registers for the MMU the 750GX main tains two identical sets of Segment Registers one for the IMMU and one for the DMMU When an instruction that updates the Segment...

Page 200: ...the translation If no match is found a TLB miss occurs Unless the access is the result of an out of order access a hardware table search operation begins if there is a TLB miss If the access is out o...

Page 201: ...require updating the real page number RPN value is passed to the memory subsystem and the WIMG bits are then used as attributes for the access Although address translation is disabled on a reset condi...

Page 202: ...lation mechanism The figure includes the checking of the N bit in the segment descriptor and then expands on the TLB Hit branch of Figure 5 6 on page 191 The detailed flow for the TLB Miss branch of F...

Page 203: ...Address Generated Continue Access to Memory Subsystem with WIMG Bits from PTE Page Table Search Operation PA 0 31 RPN A 20 31 Page Address Translation Check Page Memory Protection Violation Conditions...

Page 204: ...tinues as described in step 8 If a match is not found within the eight PTEs of the primary PTEG the address of the secondary PTEG is generated 5 The first PTE PTE0 in the secondary PTEG is read from m...

Page 205: ...H V Segment Descriptor VSID EA API 0 1 PTE C 1 Update PTE C in Memory Also Update PTE R in Memory if R_Flag 1 PTE R 1 Update PTE R in Memory Last PTE in PTEG PTE R 0 R_Flag 1 Store Operation with PTE...

Page 206: ...n cycle to perform that operation The sequencer serializes instructions to ensure the data correct ness To update the IBATs and SRs the sequencer classifies those operations as fetch serializing After...

Page 207: ...byte writes when updating only one of these bits Explicitly altering certain MSR bits using the mtmsr instruction or explicitly altering PTEs or certain system registers can have the side effect of c...

Page 208: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Memory Management Page 208 of 377 gx_05 fm 1 2 March 27 2006...

Page 209: ...rchitecture defines a means for static branch prediction as part of the instruction encoding The 750GX processor implements two types of dynamic branch prediction See Section 6 4 1 2 Branch Instructio...

Page 210: ...ral cycle length tasks to allow work to be performed on several instructions simultaneously analogous to an assembly line As an instruction is processed it passes from one stage to the next When it co...

Page 211: ...nteger unit 2 IU2 executes all integer instructions except multiplies and divides Stage The processing of instructions in the 750GX is done in stages They are fetch decode dispatch execute complete an...

Page 212: ...te that the example of a pipelined execution unit in Figure 6 1 is similar to the 3 stage FPU pipeline in Figure 6 2 Figure 6 1 Pipelined Execution Unit Figure 6 2 Superscalar Pipeline Diagram Clock 0...

Page 213: ...U Only one instruction can be dispatched to each execution unit per clock cycle There must be a vacancy in the specified execution unit reservation station A Rename Register must be available for each...

Page 214: ...that marks the point in time between the last cycle in the fetch stage and the first cycle in the execute stage Execute The operations specified by an instruction are being performed by the appropriat...

Page 215: ...propriate GPR or FPR Rename Register The results are then stored into the correct GPR or FPR during the write back stage retirement If a subsequent instruction needs the result as a source operand it...

Page 216: ...vior of some instructions Instructions are dispatched in program order an instruction in IQ1 cannot be dispatched ahead of one in IQ0 6 3 2 Instruction Fetch Timing Instruction fetch latency depends o...

Page 217: ...ache is busy due to a cache line reload operation instructions cannot be fetched until that operation completes 6 3 2 2 Cache Hit If the instruction fetch hits the instruction cache it takes only one...

Page 218: ...IU2 FPU Complete Retire Fetch LSU Dispatch Branch Instruction Queue Completion Queue Completion Queue IU1 Store Queue Processing Unit In program order Assignment In program order CQ5 CQ4 CQ3 CQ2 CQ1...

Page 219: ...d and double precision floating point add instructions to show how the number of instructions to be fetched is determined how program order is maintained by the instruction and completion queues how i...

Page 220: ...tch in IQ In dispatch entry IQ0 IQ1 Execute 2 add 3 fadd 9 add 4 b 10 add 11 add 12 fadd 9 7 fadd Complete In CQ 13 add 14 fadd 3 2 1 0 7 6 11 10 9 8 7 12 11 10 9 14 13 12 11 10 9 14 13 12 11 16 15 14...

Page 221: ...s executed but must remain in the completion queue until instruction 1 completes Instruction 3 replaces instruction 1 in the second stage of the FPU and instruc tion 6 replaces instruction 3 in the fi...

Page 222: ...in Section 6 3 2 2 Cache Hit However in this example the branch target instruction is not in either the L1 or L2 cache A cache miss extends the latency of the fetch stage so in this example the fetch...

Page 223: ...dd 10 11 8 add 1 2 3 4 5 6 7 8 0 2 add 3 fadd 9 add 4 b 10 add 11 add 12 fadd 9 3 2 1 0 7 9 8 5 4 3 2 3 2 1 0 3 2 1 3 2 1 3 6 7 6 9 8 7 6 1 0 Instruction Queue Completion Queue 5 fsub Address Data Fet...

Page 224: ...ey can be dispatched on the same cycle execute in parallel on separate execution units and could complete together and be retired together on the same cycle The completion unit maintains program order...

Page 225: ...ow control operations conditional branches unconditional branches and traps are typically expensive to execute in most machines because they disrupt normal flow in the instruction stream When a change...

Page 226: ...on is finally correctly resolved the fetched instructions are validated and allowed to complete and be retired If the prediction is resolved incorrectly then the instructions fetched are invalidated a...

Page 227: ...revious section instructions that do not update either the LR or CTR are removed from the instruction stream before they reach the completion queue either for branch taken or by removing fall through...

Page 228: ...eue and all subsequently executed instructions are purged instructions executed prior to the predicted branch are allowed to complete and instruction fetching resumes down the correct path The 750GX e...

Page 229: ...ional to Link Register bclr Fetching stops and the branch waits for the mtspr to execute An mtspr CTR followed by a Branch Conditional to Count Register bcctr Fetching stops and the branch waits for t...

Page 230: ...re 6 10 on page 231 shows cases where branch instructions are predicted It shows how both taken and not taken branches are handled and how the 750GX handles both correct and incorrect predictions The...

Page 231: ...y High Word mulhw instruction on which instruction 4 depends Figure 6 10 Branch Instruction Timing 5 fadd T3 add 4 bc 1 2 3 4 5 6 7 8 0 9 10 Fetch In dispatch entry IQ0 IQ1 Predict Execute Complete In...

Page 232: ...are shown 6 4 2 Integer Unit Execution Timing The 750GX has two integer units The IU1 can execute all integer instructions the IU2 can execute all integer instructions except multiply and divide inst...

Page 233: ...ates that the placement location and alignment of operands in memory might affect the relative performance of memory accesses and in some cases affect it significantly The effects memory operand place...

Page 234: ...d and the stores do not fall under the above categories an Enforce In Order Execution of I O eieio or Synchronize sync instruction must be used to prevent two stores from being gathered 6 4 8 System R...

Page 235: ...cations memory updates occur only on modified cache block replacements cache flushes or when one processor needs data that is modified in another s cache Therefore configuring memory as write back can...

Page 236: ...the dependent branch instruction This ensures the register values are available sooner to the branch instruction Schedule instructions so that two can be dispatched at a time Schedule instructions to...

Page 237: ...ollowing resources are required to avoid stalls in the dispatch unit IQ0 and IQ1 are the two dispatch entries in the instruction queue Requirements for dispatching from IQ0 are Needed execution unit a...

Page 238: ...18 Unless these instructions update either the CTR or the LR branch operations are folded if they are either taken or pre dicted as taken They fall through if they are not taken or pre dicted as not t...

Page 239: ...o Segment Register Indirect mtsrin 31 242 SRU 2 Execution Move to Time Base Register mttb 31 467 SRU 1 Execution Return from Interrupt rfi 19 50 SRU 2 Completion refetch System Call sc 17 1 SRU 2 Comp...

Page 240: ...ster NOR crnor 19 33 SRU 1 Execution Condition Register OR cror 19 449 SRU 1 Execution Condition Register OR with Complement crorc 19 417 SRU 1 Execution Condition Register XOR crxor 19 193 SRU 1 Exec...

Page 241: ...Multiply High Word mulhw 31 75 IU1 2 3 4 5 Multiply Low Immediate mulli 7 IU1 2 3 Multiply Low Word mullw o 31 235 IU1 2 3 4 5 NAND nand 31 476 IU1 IU2 1 Negate neg o 31 104 IU1 IU2 1 NOR nor 31 124 I...

Page 242: ...IU2 1 Execution Subtract From subf 31 40 IU1 IU2 1 Trap Word tw 31 4 IU1 IU2 2 Trap Word Immediate twi 3 IU1 IU2 2 XOR Immediate xori 26 IU1 IU2 1 XOR Immediate Shifted xoris 27 IU1 IU2 1 XOR xor 31...

Page 243: ...PU 1 1 1 Floating Negative Multiply Subtract fnmsub 63 30 FPU 2 1 1 Floating Reciprocal Estimate Single fres 59 24 FPU 2 1 1 Floating Round to Single Precision frsp 63 12 FPU 1 1 1 Floating Reciprocal...

Page 244: ...5 LSU 2 1 Load Byte and Zero with Update Indexed lbzux 31 119 LSU 2 1 Load Byte and Zero Indexed lbzx 31 87 LSU 2 1 Load Floating Point Double lfd 50 LSU 2 1 Load Floating Point Double with Update lfd...

Page 245: ...Word and Zero lwz 32 LSU 2 1 Load Word and Zero with Update lwzu 33 LSU 2 1 Load Word and Zero with Update Indexed lwzux 31 55 LSU 2 1 Load Word and Zero Indexed lwzx 31 23 LSU 2 1 Store Byte stb 38...

Page 246: ...n Store String Word Immediate stswi 31 725 LSU 2 n 3 Execution Store String Word Indexed stswx 31 661 LSU 2 n 3 Execution Store Word stw 36 LSU 2 1 Store Word Byte Reverse Indexed stwbrx 31 662 LSU 2...

Page 247: ...s the latency in finishing a single instruction the second indicates the throughput for back to back cache operations Throughput might be larger than the initial latency as more cycles might be needed...

Page 248: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Instruction Timing Page 248 of 377 gx_06 fm 1 2 March 27 2006...

Page 249: ...ddress phase of the transaction They also indicate whether a condition exists that requires the address phase to be repeated Data arbitration The 750GX uses these signals to arbitrate for data bus mas...

Page 250: ...X Signal Groups BR BG ABB TS AP 0 3 GBL TSIZ 0 2 AACK ARTY SYSCLK DBG DBWO DBB D 0 63 DP 0 7 TA DRTRY TEA INT RSRVR JTAG COP FACTORY TEST 1 1 1 1 1 5 3 4 TBST WT PLL_CFG 0 4 TT 0 4 5 5 TBEN 1 CLK_OUT...

Page 251: ...Bus Arbitration Signals The address arbitration signals are the input and output signals the 750GX uses to request the address bus recognize when the request is granted and indicate to other devices w...

Page 252: ...ssumed address bus owner ship it will not begin checking for BG again until the cycle after AACK Negation Must occur whenever the 750GX must be prevented from starting a bus transaction The 750GX will...

Page 253: ...on page 290 Timing Assertion Must occur whenever the 750GX must be prevented from using the address bus Negation May occur whenever the 750GX can use the address bus State Asserted Indicates that the...

Page 254: ...ata to be transferred On burst transfers the address bus presents the double word aligned address containing the critical code data that missed the cache on a read operation or the first double word o...

Page 255: ...ctions vary depending on whether the transaction is a memory access or an I O access State Asserted Negated Represents odd parity for each of the 4 bytes of the physical address for a transaction Odd...

Page 256: ...1 of 2 750GX Bus Master Transaction Transaction Source TT0 TT1 TT2 TT3 TT4 60x Bus Specification Command Transaction Address only1 Data Cache Block Store dcbst 0 0 0 0 0 Clean block Address only Addr...

Page 257: ...rst Single beat write Store Word Conditional Indexed stwcx 1 0 0 1 0 Write with flush atomic Single beat write N A N A 1 0 1 1 0 Reserved N A Single beat read lwarx caching inhib ited load 1 1 0 1 0 R...

Page 258: ...d N A 1 0 1 1 0 N A Read atomic Single beat read or burst 1 1 0 1 0 Clean or flush Read with intent to modify atomic Burst 1 1 1 1 0 Flush Reserved 0 0 0 1 1 N A Reserved 0 0 1 1 1 N A Read with no in...

Page 259: ...es Negated 001 1 byte Negated 010 2 bytes Negated 011 3 bytes Negated 100 4 bytes Negated 101 5 bytes1 Negated 110 6 bytes1 Negated 111 7 bytes1 1 Not generated by the 750GX State Asserted Indicates t...

Page 260: ...or page that contains the address of the current transaction Negated Indicates that a burst transfer will allocate the 750GX data cache block Timing Assertion Negation High Impedance The same as A 0 3...

Page 261: ...e M bit when the HID0 IFEM bit HID0 bit 23 is 0 and the instruction address translation bit bit 26 in the Machine State Register is 1 MSR IR 1 or if HID0 IFEM is 1 and MSR IR is 0 In either of these c...

Page 262: ...attribute signals to high impedance and sample ARTRY to determine a qualified ARTRY condition Note that the address tenure will not be terminated until the assertion of AACK even if the associated dat...

Page 263: ...to service the snooped address at that time Negated High Impedance Indicates that the 750GX does not need the snooped address tenure to be retried Timing Assertion Driven and asserted the second cycle...

Page 264: ...cancels the data tenure immediately even if the burst data has been received If the 750GX is not the address bus master this input indicates that the 750GX should immediately negate BR to allow an opp...

Page 265: ...ress tenure was pipelined on the bus before the write address tenure DBWO allows write data tenures to be run ahead of read data tenures However it does not allow write data tenures to be run ahead of...

Page 266: ...n of a bus cycle one half minimum depends on clock mode starting the cycle following the final assertion of the transfer acknowledge TA signal or following the transfer error acknowledge TEA signal or...

Page 267: ...ualified assertion of TA High Impedance Occurs on the bus clock cycle after the final assertion of TA following the assertion of TEA or in certain ARTRY cases State Asserted Negated Represents the sta...

Page 268: ...the following cycle The data tenure will remain active DBB will remain driven and the transfer termina tion signals will still be monitored by the 750GX Negated Indicates the data bus should remain d...

Page 269: ...at until new valid data with a new TA is provided While asserted DRTRY also extends the data bus tenure of the current transaction if the last or only data beat was retried and DBB has already negated...

Page 270: ...initiates an interrupt if MSR EE is set Otherwise the 750GX ignores the interrupt To guarantee that the 750GX will take the external interrupt INT must be held active until the 750GX takes the interru...

Page 271: ...sserted asynchronously to the input clocks The MCP input is negative edge sensitive Negation May be negated two bus cycles after assertion State Asserted Indicates that the 750GX must enter the checks...

Page 272: ...in Section 4 5 1 System Reset Exception 0x00100 on page 163 Output drivers are released to high impedance within five clocks after the assertion of HRESET Negated Indicates that normal operation shou...

Page 273: ...quiescent state Timing Assertion Negation Might occur on any cycle QREQ will remain asserted for the duration of the quiescent state State Asserted Indicates that all bus activity has terminated or pa...

Page 274: ...ase and decrementer should stop clocking Timing Assertion Negation May occur on any cycle The sampling of this signal is synchronous with SYSCLK State Asserted Prevents execution of a tlbsync instruct...

Page 275: ...oller asynchronously The TRST signal assures that the JTAG logic does not interfere with the normal operation of the chip and must be asserted and deasserted coincident with the assertion of the HRESE...

Page 276: ...used this phase correcting circuitry cannot be used and the I O timings are unreliable The PLL is configured by the PLL_CFG 0 4 pins These pins select the multiplier that the PLL will use to multiply...

Page 277: ...ly the processor core will be operating at an integer or half integer multiple 1 0 of the bus clock frequency Timing Assertion Negation See the IBM PowerPC 750GX RISC Microprocessor Datasheet for timi...

Page 278: ...AVDD The AVDD power signal provides power to the clock generation phase locked loop See the PowerPC 750GX Datasheet for information on how to use this signal GND and OGND The GND and OGND signals prov...

Page 279: ...che snoop copy back address buffer associated data block buffer located in cache Reservation address buffer for snoop monitoring L2 castout buffer Pipeline collision detection for data cache buffers R...

Page 280: ...xecution units at a peak rate of two instructions per clock Conversely load and store instructions explicitly specify the movement of operands to and from the integer and Floating Point Register files...

Page 281: ...ed read access hits a modified line in the cache Since the 750GX data cache tags are single ported simultaneous load or store and snoop accesses cause resource contention Snoop accesses have the highe...

Page 282: ...a depen dency exists In addition the 750GX can be configured to reorder high priority store operations ahead of lower priority store operations Because the processor can dynamically optimize run time...

Page 283: ...access instructions or data in a direct store segment will result in the 750GX taking an instruction storage interrupt ISI or data storage interrupt DSI exception Figure 8 2 Timing Diagram Legend A s...

Page 284: ...re also shows a data transfer that consists of a single beat transfer of as many as 64 bits Four beat burst transfers of 32 byte cache lines require data transfer termination signals for each beat of...

Page 285: ...tion To begin the data tenure the 750GX arbitrates for mastership of the data bus Transfer After the 750GX is the data bus master it samples the data bus for read operations or drives the data bus for...

Page 286: ...for a second miss until the first miss is reloaded The MuM feature enables a second request queue to the L2 cache for handling up to four misses If there is a hit in the L2 cache for a data cache miss...

Page 287: ...rallelism on the bus 8 2 2 1 Miss under Miss and System Performance The MuM feature allows loads and stores that miss in the L1 cache to continue to the L2 cache even though the L1 cache is busy reloa...

Page 288: ...loads to a different cache line until the outstanding load miss is com plete The MuM feature does not look deeper into the load store request queue for other loads that do not reference the same cache...

Page 289: ...bi TLB Invalidate Entry tlbie and eieio instructions stall MuM requests These instructions represent special cache and synchronizing mechanisms that will prevent MuM requests from starting until they...

Page 290: ...led However the MuM reload is loaded into the L2 cache if enabled 8 3 Address Bus Tenure This section describes the three phases of the address tenure address bus arbitration address transfer and addr...

Page 291: ...on pending Typically bus parking is provided to the device that was the most recent bus master However system designers might choose other schemes such as providing unrequested bus grants in situation...

Page 292: ...er to enforce cache coherency see the discussion of snooping in Section 8 3 3 Address Transfer Termination on page 300 The signals used in the address transfer include the following signal groups Addr...

Page 293: ...er s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor gx_08 fm 1 2 March 27 2006 Bus Interface Operation Page 293 of 377 Figure 8 8 Address Bus Transfer 0 1 2 3 4 qual BG TS ABB ADDR aack artry_...

Page 294: ...Transfer Attribute Signals on page 255 describes the encodings for the address transfer attribute signals Transfer Type TT 0 4 Signals Snooping logic should fully decode the transfer type signals if t...

Page 295: ...nsaction is an instruction fetch WT negated or a data read operation WT asserted Cache Inhibit CI Signal The 750GX indicates the caching inhibited status of a transaction determined by the setting of...

Page 296: ...at DW1 U DW2 U DW3 U DW0 U Fourth data beat DW1 L DW2 L DW3 L DW0 L Fifth data beat DW2 U DW3 U DW0 U DW1 U Sixth data beat DW2 L DW3 L DW0 L DW1 L Seventh data beat DW3 U DW0 U DW1 U DW2 U Eighth dat...

Page 297: ...alf word read from an odd byte aligned address An attempt to address data that crosses a word bound ary requires two bus transfers to access the data Due to the performance degradations associated wit...

Page 298: ...sfer Size Four Bytes TSIZ 0 2 A 29 31 Data Bus Byte Lanes 0 1 2 3 4 5 6 7 Aligned 1 0 0 0 0 0 A A A A Misaligned first access 0 1 1 0 0 1 A A A second access 0 0 1 1 0 0 A Misaligned first access 0 1...

Page 299: ...bit bus mode Table 8 7 Misaligned 32 Bit Data Bus Transfer 4 Byte Examples Transfer Size Four Bytes TSIZ 0 2 A 29 31 Data Bus Byte Lanes 0 1 2 3 4 5 6 7 Aligned 1 0 0 0 0 0 A A A A x x x x Misaligned...

Page 300: ...is required the ARTRY response will be asserted by a bus snooping device as early as the second cycle after the assertion of TS Once asserted ARTRY must remain asserted through the cycle after the ass...

Page 301: ...Bus Arbitration Data bus arbitration uses the data arbitration signal group DBG DBWO and DBB Additionally the combi nation of TS and TT 0 4 provides information about the data bus request to external...

Page 302: ...s left to the masters Optionally the memory system can control data tenure scheduling directly with DBG However it is possible to ignore the DBB signal in the system if the DBB input is not used as th...

Page 303: ...Effect of Alignment in Data Transfers on page 296 Burst operations always transfer eight words and are aligned on 8 word address boundaries Burst transfers can achieve significantly higher bus through...

Page 304: ...cted where no DRTRY mode cancels checking the cycle after TA The assertion of TEA termi nates the data tenure immediately even if in the middle of a burst However it does not prevent incorrect data th...

Page 305: ...n which TA is asserted need not be consecutive thus allowing pacing of the data transfer beats For read bursts to terminate successfully TEA and DRTRY must remain negated during the transfer For write...

Page 306: ...le later confirmed with the negation of DRTRY The DRTRY signal is valid only for read transactions TA must be asserted on the bus clock cycle before the first bus clock cycle of the assertion of DRTRY...

Page 307: ...50GX Note The 750GX does not implement a synchronous error capability for memory accesses This means that the exception instruction pointer saved into Machine Status Save Restore Register 0 SRR0 does...

Page 308: ...ooped When other devices detect the GBL input asserted they must respond by snooping the broadcast address Normally GBL reflects the M bit value specified for the memory reference in the corresponding...

Page 309: ...put By delaying the data bus tenure the latency increases but because of split transaction pipe lining the overall throughput is not affected unless the data bus latency causes the third address tenur...

Page 310: ...erface Operation Page 310 of 377 gx_08 fm 1 2 March 27 2006 Figure 8 17 Fastest Single Beat Reads BR BG ABB TS A 0 31 TT 0 4 TBST GBL AACK ARTRY DBG DBB D 0 63 TA DRTRY TEA 1 2 3 4 5 6 7 8 9 10 11 12...

Page 311: ...18 illustrates the fastest single beat writes supported by the 750GX All bidirectional signals are tristated between bus tenures Figure 8 18 Fastest Single Beat Writes BR BG ABB TS A 0 31 TT 0 4 TBST...

Page 312: ...erted in clock cycle 6 In the third access DRTRY is asserted in clock cycle 11 to flush the previous data Note All bidirectional signals are tristated between bus tenures The pipelining shown in Figur...

Page 313: ...sfers are delayed in the following ways The TA signal is held negated to insert wait states in clocks 3 and 4 In clock 6 DBG is held negated delaying the start of the data tenure The last access is no...

Page 314: ...rite burst shows the use of TA signal negation to delay the third data beat The final read burst shows the use of DRTRY on the third data beat The address for the third transfer is delayed until the f...

Page 315: ...burst in clock 0 is the critical quadword The TEA signal truncates the burst write transfer on the third data beat The 750GX eventually causes an exception to be taken on the TEA event Figure 8 22 Use...

Page 316: ...se transactions do not assert the TBST signal even though a two beat burst may be performed having the same TBST and TSIZ 0 2 encodings as the 64 bit data bus mode Single beat data transactions are pe...

Page 317: ...ple of a two beat data transfer with DRTRY asserted during each data tenure is shown in Figure 8 24 Figure 8 23 32 Bit Data Bus Transfer 8 Beat Burst Figure 8 24 32 Bit Data Bus Transfer 2 Beat Burst...

Page 318: ...s the 750GX to hold any loaded data at the bus interface for one additional bus clock to verify that the data is valid before forwarding it to the internal CPU For systems that do not imple ment the D...

Page 319: ...sing shared addresses that could be changed in the MMU tables by the 750GX during the DMA master s tenure The TLBISYNC input when asserted to the 750GX prevents the 750GX from completing any instructi...

Page 320: ...tenure from the same 750GX In general an address tenure on the bus is followed strictly in order by its associated data tenure Transac tions pipelined by the 750GX complete strictly in order However t...

Page 321: ...WO Any number of bus transactions by other bus masters can be attempted between any of these steps Note the following regarding DBWO DBWO can be asserted if no data bus read is pending but it has no e...

Page 322: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Bus Interface Operation Page 322 of 377 gx_08 fm 1 2 March 27 2006...

Page 323: ...configuration Double bit error machine check Global invalidation of L2 contents Write through operation L2 test support L2 locking by way Data only and instruction only modes 9 2 L2 Cache Operation Th...

Page 324: ...ges in the L2 cache and are forwarded on the 60x bus interface Cacheable single beat store requests marked copy back that hit in the L2 cache are allowed to update the L2 cache sector but do not cause...

Page 325: ...the cache are locked Any combination of ways can be locked The effect of locking on the replacement algorithm is that the least recently used of the unlocked ways is chosen for replacement Table 9 3...

Page 326: ...and 750GL RISC Microprocessor L2 Cache Page 326 of 377 gx_09 fm 1 2 March 27 2006 110 x011 1 1x1 xxx0 3 1x1 xx01 2 101 0x11 0 111 x011 1 Table 9 3 Effect of Locked Ways on LRU Interpretation Page 2 o...

Page 327: ...Unit Data Out Request Data In Request 8 bit 64 bit L2 SRAM 1 MB ECC ECC ECC ECC 64 bit 64 bit Store Queue ST0 ST1 3 Lines L2 Reload Queue 2 Lines L1 Data Cache Castout Single Beat Stores L1 Data Load...

Page 328: ...ush from the L2 cache to the 60x bus as required If the dcbf and dcbst instructions do not cause a sector push from the L2 cache they are forwarded to the 60x bus interface for address only broadcast...

Page 329: ...lobal invalidation function in which all bits of the L2 tags tag data bits tag status bits and LRU bit are cleared It is performed by an on chip hardware state machine that sequentially cycles through...

Page 330: ...be deallocated for line replacement The locked L2 cache is intended to be a local memory for the processor and so should not contain addresses that are accessed outside the processor However the L2 c...

Page 331: ...one of the unlocked ways of the cache by the new block of data or instructions received from the bus or from the L1 cache in the case of a castout If all ways are locked an L2 miss causes the new blo...

Page 332: ...esolution during L2 cache testing 9 8 1 L2CR Support for L2 Cache Testing L2CR DO and L2CR TS support the testing of the L2 cache L2CR DO prevents instructions from being cached in the L2 This allows...

Page 333: ...ing the potential for bus errors due to addressing hardware or nonexistent memory The L2 cache then can be further verified by reading the previously loaded addresses and observing whether all the tag...

Page 334: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor L2 Cache Page 334 of 377 gx_09 fm 1 2 March 27 2006...

Page 335: ...gible power when they are not switching stopping the clock to an execution unit effectively eliminates its power consumption The operation of DPM is completely transparent to software or any external...

Page 336: ...t interrupt Hard or soft reset Nap Bus snooping enabled by deas sertion of QACK Decrementer timer Controlled by hardware and software External asynchronous exceptions1 Decrementer interrupt Hard or so...

Page 337: ...s snooping logic and the time base decrementer are still enabled Doze mode is enabled with the following sequence 1 Set the doze bit HID0 8 1 clear the nap and sleep bits HID0 9 and HID0 10 0 2 750GX...

Page 338: ...g could be used by the system at any time with knowledge of what power management mode the 750GX is in currently if any Nap mode can be summarized as follows Time base decrementer still enabled Therma...

Page 339: ...is no longer necessary it asserts QACK and the 750GX will enter sleep mode Sleep mode can be summarized as follows All functional units disabled including bus snooping and time base decrementer All no...

Page 340: ...source of the processor clock at any given time In addition the supplied processor voltage VDD can be varied to support the selected frequency lower voltage lower frequency and lower power for normal...

Page 341: ...gured to be off the proce dure for switching to PLL0 as the selected PLL involves changing the configuration and range bits waiting for lock and then selecting PLL0 as described in the previous paragr...

Page 342: ...ged just before or just after that common rising edge to achieve seamless switching The PLL select logic in Figure 10 2 represents the logic needed to generate the MUX control signal When HID1 is writ...

Page 343: ...constant from the junction to the case can be large and accuracy can be a problem This might lead to lower overall system performance due to the necessary compensation to alleviate measurement deficie...

Page 344: ...egister at the factory Note that all the bits in THRM1 THRM2 and THRM3 are cleared to 0 during a hard reset THRM4 always contains the fused offset value determined at the factory The TAU remains idle...

Page 345: ...ate that the TIN bit state is valid If the threshold value has been crossed the THRMn TIN and THRMn TIV bits are set to 1 and a thermal management interrupt is gener ated if both the THRMn TIE and MSR...

Page 346: ...Rs 10 4 2 3 750GX Junction Temperature Determination While the 750GX s TAU does not implement an analog to digital converter to enable the direct determination of the junction temperature system softw...

Page 347: ...d TOFFSET 10 5 Instruction Cache Throttling The 750GX provides an instruction cache throttling mechanism to effectively reduce the instruction execution rate without the complexity and overhead of dyn...

Page 348: ...4 ICTC Bit Field Settings Bits Name Description 0 22 Reserved Bits reserved for future use The system software should always write zeros to these bits when writing to the THRM SPRs 23 30 FI Instructio...

Page 349: ...errupt functions and select events to count UMMCR0 UMMCR1 provide user level read access to these registers The Sampled Instruction Address Register SIA contains the effective address of an instructio...

Page 350: ...mfspr instructions Table 11 1 Performance Monitor SPRs SPR Number SPR 5 9 SPR 0 4 Register Name Access Level 952 11101 11000 MMCR0 Supervisor 953 11101 11001 PMC1 Supervisor 954 11101 11010 PMC2 Super...

Page 351: ...C3 and PMC4 Corresponding events to the MMCR1 bits are described in Section 11 2 1 5 Performance Monitor Counter Registers PMCn on page 351 MMCR1 can be accessed with the mtspr and mfspr instructions...

Page 352: ...ed through RTCSELECT MMCR0 7 8 00 31 01 23 10 19 11 15 0000100 Number of instructions dispatched 0 1 or 2 instructions per cycle 0000101 Number of Enforce In Order Execution of I O eieio instructions...

Page 353: ...elect Encodings Page 1 of 2 Encoding Description 0 0000 Register holds current value 0 0001 Number of processor cycles 0 0010 Number of completed instructions not including folded branches 0 0011 Numb...

Page 354: ...PMC4 Events MMCR1 5 9 Select Encodings Encoding Comments 00000 Register holds current value 00001 Number of processor cycles 00010 Number of completed instructions not including folded branches 00011...

Page 355: ...ltiple processes and because statistics on only a particular process might be of interest a facility is provided to mark a process The performance monitor PM bit MSR 29 is used for this purpose System...

Page 356: ...first five events are common to all four counters and are considered to be reference events These are as follows 00000 Register holds current value 00001 Number of processor cycles 00010 Number of com...

Page 357: ...A DSI on a data access does not complete the interrupting instruction 11 7 JTAG COP Functions 11 7 1 Introduction The 750GX implements the Joint Test Action Group JTAG and common on chip processor CO...

Page 358: ...t Registers Instruction Block Address Translation BAT Registers External memory INTMEM will allow reading and writing the above arrays while accessing a chain shorter than the LSRL INTMEM is a proper...

Page 359: ...T For a hard reset to recover from a hardware problem like a checkstop only 255 bus clock cycles are neces sary to initialize the state of the processor provided the PLL remains locked During hard res...

Page 360: ...e 360 of 377 gx_11 fm 1 2 March 27 2006 11 8 3 Reset Sequence Figure 11 2 Reset Sequence Hard Reset Scan in 0s Hard Reset yes no JTAG_IR FFRZ no yes Stop Chip Clks Perform RISCWatch Functions RISCWatc...

Page 361: ...IN 11 9 2 Checkstop Control Bits Some of the checkstop sources can be controlled via Hardware Implementation Dependent Register 0 HID0 and the L2CR register bits Table 11 6 HID0 Checkstop Control Bits...

Page 362: ...the processor that is being replaced needs to go through the same hard reset sequence as the replacement processor With SYSCLK running the checkstop power consumption of the 750GX should be similar t...

Page 363: ...che and tag L1 data cache and tag and L2 tag If parity checking is enabled and bad parity is found on a read for the enabled array then the MSR ME bit controls the action taken by the processor for th...

Page 364: ...ts for the desired arrays in the HID2 Register ICPE DCPE and L2PE for the ICache ITag DCache DTag and L2Tag respectively Parity errors are reported with the parity status bits in the HID2 Register ICP...

Page 365: ...us unit ID CMOS complementary metal oxide semiconductor COP common on chip processor CQ completion queue CR Condition Register CTR Count Register DABR Data Address Breakpoint Register DAR Data Address...

Page 366: ...er IEEE Institute for Electrical and Electronics Engineers IMMU instruction MMU IQ instruction queue ITLB instruction translation lookaside buffer IU integer unit JTAG Joint Test Action Group L2 secon...

Page 367: ...entry group PVR Processor Version Register RAW read after write RISC reduced instruction set computing RTL register transfer language RWITM read with intent to modify RWNITM read with no intent to mod...

Page 368: ...ue UISA user instruction set architecture UMMCRn User Monitor Mode Control Registers UPMCn User Performance Monitor Counter Registers USIA User Sampled Instruction Address Register VEA virtual environ...

Page 369: ...ough 226 Branch folding 226 Branch instructions address calculation 106 condition register logical 107 list of instructions 107 system linkage 108 118 trap 108 Branch prediction 209 229 Branch process...

Page 370: ...sfer termination 268 303 Data cache configuration 123 DCFI DCE DLOCK bits 132 organization 123 Data organization in memory 82 Data transfers alignment 296 burst ordering 295 eciwx and ecowx instructio...

Page 371: ...y bit G bit 125 H I J K HIDn hardware implementation dependent registers HID0 description 65 doze bit 337 DPM enable bit 337 nap bit 338 HID1 description 70 PLL configuration 277 HRESET hard reset sig...

Page 372: ...tructions 104 floating point move instructions 98 floating point store instructions 105 integer load instructions 99 integer store instructions 101 latency load store instructions 244 load store multi...

Page 373: ...172 351 Power and ground signals 278 Power management doze mode 337 dynamic power management 335 full power mode 337 nap mode 337 programmable power modes 336 sleep mode 339 software considerations 34...

Page 374: ...ption 61 SR manipulation instructions 119 Segmented memory model see Memory management unit Serializing instructions 225 Shift rotate instructions 95 SIA sampled instruction address register 75 172 35...

Page 375: ...Timing instruction BPU execution timing 225 branch timing example 231 cache hit 220 cache miss 223 execution unit 225 FPU execution timing 232 instruction dispatch 224 instruction flow 215 instructio...

Page 376: ...User s Manual IBM PowerPC 750GX and 750GL RISC Microprocessor Index Page 376 of 377 750gx_umIX fm 1 2 March 27 2006...

Page 377: ...anged the number Two to Four in the second subbullet in the bullet list On page 279 rewrote the first paragraph after the bullet list On page 286 rewrote the first paragraph in Section 8 2 2 Miss Unde...

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