Chapter 2. Architecture and technical overview
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Table 2-2 SMT levels that are supported by POWER processors
The architecture of the POWER8 processor, with its larger caches, larger cache bandwidth,
and faster memory, allows threads to have faster access to memory resources, which
translates in to a more efficient usage of threads. Because of that, POWER8 allows more
threads per core to run concurrently, increasing the total throughput of the processor and of
the system.
2.2.4 Memory access
On the Power E870 and Power E880, each POWER8 processor has two memory controllers,
each connected to four memory channels. Each memory channel operates at 1600 MHz and
connects to a DIMM. Each DIMM on a POWER8 system has a memory buffer that is
responsible for many functions that were previously on the memory controller, such as
scheduling logic and energy management. The memory buffer also has 16 MB of level 4 (L4)
cache.
On the Power E870 each memory channel can address up to 64 GB. Therefore a single
system node can address 2 TB of memory. A two node system can address up to 4 TB of
memory.
On the Power E880 each memory channel can address up to 128 GB. Therefore a single
system node can address 4 TB of memory. A two node system can address up to 8 TB of
memory and a four node system can address up to 16 TB of memory.
Technology
Cores/system
Maximum SMT mode
Maximum hardware
threads per system
IBM POWER4
32
Single Thread (ST)
32
IBM POWER5
64
SMT2
128
IBM POWER6
64
SMT2
128
IBM POWER7
256
SMT4
1024
IBM POWER8
192
SMT8
1536
