5137ch02.fm
Draft Document for Review October 14, 2014 10:19 am
38
IBM Power Systems E870 and E880 Technical Overview and Introduction
The following are additional features that can augment the performance of the POWER8
processor:
Support for DDR3 and DDR4 memory through memory buffer chips that offload the
memory support from the POWER8 memory controller.
Each memory CDIMM has 16 MB of L4 cache within the memory buffer chip that reduces
the memory latency for local access to memory behind the buffer chip; the operation of the
L4 cache is not apparent to applications running on the POWER8 processor. Up to 128
MB of L4 cache can be available for each POWER8 processor.
Hardware transactional memory.
On-chip accelerators, including on-chip encryption, compression, and random number
generation accelerators.
Coherent Accelerator Processor Interface, which allows accelerators plugged into a PCIe
slot to access the processor bus using a low latency, high-speed protocol interface.
Adaptive power management.
There are two versions of the POWER8 processor chip. Both chips use the same building
blocks. The scale-out systems use a 6-core version of POWER8. The 6-core chip is installed
in pairs in a Dual Chip Module (DCM) that plugs into a socket in the system board of the
systems. Functionally, it works as a single chip module (SCM).
Figure 2-7 shows a graphic representation of the 6-core processor. A 6-core processor is only
available on the scale-out systems. It is shown here for informational purposes.
Figure 2-7 6-core POWER8 processor chip
