IBM DDRS-39130 - Ultrastar 9.1 GB Hard Drive, Specifications

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SCAM level, SCAM level control bits, specify the SCAM function level to be supported. (shipping
default = 2)
ARHES (Automatic Reassign Hard Error Sites) bit of one indicates the drive will automatically reassign
an hard read error. The error will be recovered when the LBA is written. ARHES bit of zero indicates
the drive will not automatically recover hard read error.
CMDAC (Command Active) bit determines in conjunction with LED Mode bits if an L E D on the file is
activated while commands are active. If C M D A C bit is one and L E D bits are zero, an L E D driver is
active when a command is queued or executed.
CPE (Concurrent Processing Enable) bit is allowed to be modified by the initiator for host system device
driver compatibility. Read(6), Read extend(10), Write(6), Write extend(10), untagged and unlinked
Request Sense or Inquiry can be executed concurrently in both CPE bit set to 0 and 1.
CAEN When set this bit causes the Command Age Limit timer to be used to avoid commands waiting
in the command queue for an indefinite period. When commands have been in the queue for a period of
time greater than the timer limit they will be re-ordered to be executed in on a first come first served
basis. When this bit is reset commands are always executed based on the queue re-ordering rules.
IGRA (Ignore Reassigned LBA) bit is set to 1 for preventing the drive from reassign processing against
reassigned LBA when R C bit (Mode Page 1 byte 2 bit 4) is active. The main purpose of this bit is to
avoid undesirable read processing time delay due to reassigned LBA processing for continuous data
availability requirements such as Audio Visual application. I G R A bit is set to 0 specifies the drive shall
process reassigned LBA even if R C bit is active.
AVERP (AV E R P Mode) bit is set to one in order to specify maximum retry counts during D R P and
command execution time limit. When AVERP bit is set to one, the maximum retry counts for read and
write operations are specified by Read Retry Count (Mode Page 1 Byte 3) and Write Retry Count
(Mode Page 1 Byte 8) respectively. Recovery Time Limit (Mode Page 1 Byte 10 and 11) is effective to
limit the command execution time. AVERP bit is set to zero for ignoring Recovery Time Limit value
and for specifying that the drive shall process D R P up to the default maximum retry count when Read
Retry Count and Write Retry Count are set to non-zero value. *
EADM, Enable Automatic Drive Maintenance bit, is set to one to indicate that the A D M function is
enabled to enhance reliability in continuous usage. The E A D M bit of zero disables the A D M function.
Default is zero.
ADC (Adaptive Cache Enable), when set, allows the drive to modify the read-ahead caching algorithm,
ignoring parameters in Page 8. The adaptation is based on analyzing the most recent command history
and the current contents of the cache buffers.
LED Mode is designed to control the operation of a file L E D driver.
−
L E D Mode = 0000b
The C M D A C bit controls the LED.
C M D A C = 1 (Command Active)
C M D A C = 0 (Motor Active)
−
L E D Mode = 0001b (Motor Active)
When the motor is spinning, the L E D is high.
−
L E D Mode = 0010b (Command Active).
Bit 2 Bit 1 SCAM function
0 0 Disable
0 1 SCAM level 1
1 0 SCAM level 2
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O E M Spec. of DDRS-3xxxx