30
Plasma TV Service Manual
14/03/2005
(controlled by subaddresses 84H and 85H)
V
DDA1A
L1
P
analog supply voltage for analog inputs AI1x (3.3 V)
AGNDA
L2
P
analog signal ground
AI14
L3
I
analog input 14
V
SSD9
L4
P
digital ground 9 (peripheral cells)
V
SSD10
L5
P
digital ground 10 (core)
ADP6
L6
O
MSB - 2 of direct analog-to-digital converted output data
(VSB)
ADP3
L7
O
MSB - 5 of direct analog-to-digital converted output data
(VSB)
V
SSD11
L8
P
digital ground 11 (peripheral cells)
V
SSD12
L9
P
digital ground 12 (core)
RTCO
L10
O/st/pd
real-time control output; contains information about actual
system clock frequency, field rate, odd/even sequence,
decoder status, subcarrier frequency and phase and PAL
sequence; the RTCO pin is enabled via I
2
C-bus bit RTCE;
see notes 5, 6
V
SSD13
L11
P
digital ground 13 (peripheral cells)
ITRI
L12
I/(O)
image port output control signal, affects all input port pins
inclusive ICLK, enable and active polarity is under software
control (bits IPE in subaddress 87H); output path used for
testing: scan output
IDQ
L13
O
output data qualifier for image port (optional: gated clock
output)
IGP0
L14
O
general purpose output signal 0; image port (controlled by
subaddresses 84H and 85H)
AOUT
M1
O
analog test output (do not connect)
V
SSA0
M2
P
ground for internal Clock Generation Circuit (CGC)
V
DDA0
M3
P
analog supply voltage (3.3 V) for internal clock generation
circuit
V
DDD9
M4
P
digital supply voltage 9 (peripheral cells)
V
DDD10
M5
P
digital supply voltage 10 (core)
ADP7
M6
O
MSB
1 of direct analog-to-digital converted output data
(VSB)
ADP2
M7
O
MSB
6 of direct analog-to-digital converted output data
(VSB)
V
DDD11
M8
P
digital supply voltage 11 (peripheral cells)
V
DDD12
M9
P
digital supply voltage 12 (core)
RTS0
M10
O
real-time status or sync information, controlled by
subaddresses 11H and 12H
V
DDD13
M11
P
digital supply voltage 13 (peripheral cells)
AMXCLK
M12
I
audio master external clock input
FSW
M13
I/pd
fast switch (blanking) with internal pull-down inserts
component inputs into CVBS signal
ICLK
M14
I/O
clock output signal for image port, or optional
asynchronous back-end clock input
TEST13
N1
NC
do not connect, reserved for future extensions and for testing
TEST14
N2
I/pu
do not connect, reserved for future extensions and for testing
TEST15
N3
I/pd
do not connect, reserved for future extensions and for testing
CE
N4
I/pu
chip enable or reset input (with internal pull-up)
LLC2
N5
O
line-locked 1 ¤2 clock output (13.5 MHz nominal)
CLKEXT
N6
I
external clock input intended for analog-to-digital conversion
of VSB signals (36 MHz)
ADP5
N7
O
MSB - 3 of direct analog-to-digital converted output data
(VSB)
ADP0
N8
O
LSB of direct analog-to-digital converted output data (VSB)
SCL
N9
I
serial clock input (I 2 C-bus)
RTS1
N10
O
real-time status or sync information, controlled by
subaddresses 11H and 12H
ASCLK
N11
O
audio serial clock output
ITRDY
N12
I
target ready input for image port data
TEST16
N13
NC
do not connect, reserved for future extensions and for testing
TEST17
N14
NC
do not connect, reserved for future extensions and for testing
TEST18
P2
I/O
do not connect, reserved for future extensions and for testing
Summary of Contents for HPT-4205
Page 1: ...42 PLASMA TV Built in Tuner SERVICE MANUAL...
Page 56: ...54 Plasma TV Service Manual 14 03 2005 15 CIRCUIT DIAGRAMS...
Page 57: ...55 Plasma TV Service Manual 14 03 2005...
Page 58: ...56 Plasma TV Service Manual 14 03 2005...
Page 59: ...57 Plasma TV Service Manual 14 03 2005...
Page 60: ...58 Plasma TV Service Manual 14 03 2005...
Page 61: ...59 Plasma TV Service Manual 14 03 2005...
Page 62: ...60 Plasma TV Service Manual 14 03 2005...
Page 63: ...61 Plasma TV Service Manual 14 03 2005...