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11
Plasma TV Service Manual
14/03/2005
P3.2/ADC2
11
I/O
P3.3/ADC3
12
I/O
P3.4/PWM7
30
I/O
output for 6-bit PWM7
V
SSC
13
I/O
core ground
Port 0: 8-bit programmable bidirectional port
SCL(NVRAM)
14
I
I
2
C-bus Serial Clock input to Non-Volatile RAM
SDA(NVRAM)
15
I/O
I
2
C-bus Serial Data input/output (Non-Volatile RAM)
P0.2
16
I/O
input/output for general use
P0.3
17
I/O
input/output for general use
P0.4
18
I/O
input/output for general use
P0.5
19
I/O
8 mA current sinking capability for direct drive of Light Emitting
Diodes (LEDs)
P0.6
20
I/O
P0.7
21
I/O
input/output for general use
V
SSA
22
-
analog ground
CVBS0
23
I
Composite Video Baseband Signal (CVBS) input; a positive-going
1V
CVBS1
24
I
(peak-to-peak) input is required; connected via a 100 nF capacitor
SYNC_FILTER
25
I
sync-pulse-filter input for CVBS; this pin should be connected to
V
SSA
via a 100 nF capacitor
IREF
26
I
reference current input for analog circuits; for correct operation a 24
resistor should be connected to
V
SSA
FRAME
27
O
Frame de-interlace output synchronized with the VSYNC pulse to
produce a non-interlaced display by adjustment of the vertical
deflection circuits
TEST
28
I
not available; connect this pin to
V
SSA
COR
29
O
contrast reduction: open-drain, active LOW output which allows
selective contrast reduction of the TV picture to enhance a mixed
mode display
30
I/O
P3.4/PWM7 (described above)
V
DDA
31
-
analog supply voltage (3.3 V)
B
32
O
Blue colour information pixel rate output
G
33
O
Green colour information pixel rate output
R
34
O
Red colour information pixel rate output
VDS
35
O
video/data switch push-pull output for pixel rate fast blanking
HSYNC
36
I
horizontal sync pulse input: Schmitt triggered for a Transistor
Transistor Level (TTL) version; the polarity of this pulse is
programmable by register bit TXT1.H POLARITY
VSYNC
37
I
vertical sync pulse input; Schmitt triggered for a TTL version; the
polarity of this pulse is programmable by register bit TXT1.V
POLARITY
V
SSP
38
-
periphery ground
V
DDC
39
-
core supply voltage (+3.3 V)
OSCGND
40
-*
crystal oscillator ground
XTALIN
41
I
12 MHz crystal oscillator input
XTALOUT
42
O
12 MHz crystal oscillator output
RESET
43
I
reset input; if this pin is HIGH for at least 2 machine cycles (24
oscillator periods) while the oscillator is running, the device resets;
this pin should be connected to
V
DDP
via a capacitor
V
DDP
44
-
periphery supply voltage (+3.3 V)
Port 1: 8-bit programmable bidirectional port
P1.0
45
I/O
input/output for general use
P1.1
46
I/O
input/output for general use
P1.2
47
I/O
input/output for general use
P1.3
48
I/O
input/output for general use
SCL
49
I
I
2
C-bus Serial Clock input from application
Summary of Contents for HPT-4205
Page 1: ...42 PLASMA TV Built in Tuner SERVICE MANUAL...
Page 56: ...54 Plasma TV Service Manual 14 03 2005 15 CIRCUIT DIAGRAMS...
Page 57: ...55 Plasma TV Service Manual 14 03 2005...
Page 58: ...56 Plasma TV Service Manual 14 03 2005...
Page 59: ...57 Plasma TV Service Manual 14 03 2005...
Page 60: ...58 Plasma TV Service Manual 14 03 2005...
Page 61: ...59 Plasma TV Service Manual 14 03 2005...
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Page 63: ...61 Plasma TV Service Manual 14 03 2005...