3. System power switch turns on bulk power supplies and fans, and releases RESET on all processors
simultaneously, when toggled on.
5. Initial processor firmware code fetch is PAL code from EEPROM in PDH, retrieved 4 bytes at a time by
DMDC in ICH10 (No shared memory or I/O devices are available at this time; for example they are not
initially configured).
5. Firmware code stack is initially in BBRAM in PDH, retrieved 4 byes at a time, through PDH and DMD
buses.
5. PAL code configures all processors.
5. SAL code configures all platform ICH10 chips, including shared memory and all responding I/O
devices.
5. Firmware code and stack are relocated to shared memory, after all x4 DIMM ranks in shared memory
are configured and tested.
5. UEFI Shell is launched from shared memory, and cache lines are retrieved 128 bytes at a time by
MEMC in ICH10.
6. OS loader is launched using the UEFI device driver.
6. OS boots and starts its own device drivers.
6. OS can use runtime PAL and SAL calls, and APCI features (these abstraction layers enable platform
independence).
Troubleshooting the firmware
Cause
The server has the following sets of firmware installed:
• System firmware
• iLO 3 firmware
• I/O card firmware
◦ Fibre Channel cards
◦ SAS HBA cards
◦ LAN cards
• SAS controller firmware
• SAS HDD firmware
• LOM firmware
System firmware and iLO 3 firmware must be from the same release. Independent updates are not
supported. Details about a specific release are available in the associated Release Notes.
Firmware updates are available from the Hewlett Packard Enterprise website at
under "Support and Drivers".
Identifying and troubleshooting firmware issues
Erratic system operation, or the fact that the server might not boot successfully to the UEFI Boot Manager
or to the UEFI Shell, are symptoms of possible firmware issues.
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Troubleshooting the firmware
