5
Peripheral devices are connected to the CPU by interface cards installed in the I/O card cages present in the CPU
and optional I/O extender chassis. Each slot in the card cage is assigned an address, called a
select code
, that
may be referenced by I/O instructions in the base set. Select codes range from 0 to 77 octal, with the first eight
select codes reserved for the system, providing connections for 56 possible interfaces.
The 211x machines use a hardwired processor providing 70 basic instructions and up to 32K of core memory. The
base instruction set is divided into the Memory Reference Group, the Shift-Rotate Group, the Alter-Skip Group, and
the I/O Group. SRG instruction words may contain from one to four suboperation codes that are executed from left-
to-right, and ASG instruction words may contain from one to eight suboperations. An optional Extended Arithmetic
Unit may be added to the 2115 and 2116 that provides hardware multiply and divide, double-load and -store, and
double-word shift and rotate instructions.
The 2100 machine uses a microprogrammed processor that provides the 80 instructions of the base set and the
EAU as standard equipment. Optional floating-point microcode adds six two-word single-precision instructions.
User microprogramming is also supported. When used as part of an HP 2000 Time-Shared BASIC system, the
CPU designated as the I/O processor may be equipped with microcode implementing 18 additional OS accelerator
instructions.
The 1000 M/E-Series machines also use microprogrammed processors and extend the 2100 instruction set with
two new index registers, X and Y, and a new Extended Instruction Group consisting of 32 index-register instructions
and 10 word-and-byte-manipulation instructions. The six 2100 floating-point instructions are also standard. The
1000 F-Series adds a hardware floating-point processor with 18 new triple- and quad-word instructions. A number
of new optional microcode extensions are available with the M/E/F-Series.
The 21xx and 1000 machines provide Direct Memory Access and Dual-Channel Port Controller options,
respectively, for high-speed I/O transfers. The 2114 supports a single DMA channel; all other machines support
two DMA or DCPC channels.
1000 CPUs offer the optional Dynamic Mapping System, which provides memory mapping on a page-by-page
basis. The 5-bit page number of a logical memory address selects one of 32 ten-bit map registers containing
physical page numbers. The ten-bit page number combined with the ten-bit page offset yields a 20-bit physical
address capable of accessing a location in a one-megaword memory. DMS provides separate maps for system
and user programs, as well as for the two DCPC channels, and includes microcode that implements the 38
Dynamic Mapping Instructions used to manipulate the mapping system.
Optional memory protection is accomplished by dividing the logical address space into protected and unprotected
parts. When protection is enabled, any attempt to write below the fence separating the two parts is inhibited, and
an interrupt to the operating system occurs, which aborts the offending user program. If the DMS option is enabled
as well, protection is enhanced by specifying read and write permissions on a page-by-page basis.
This implementation is a simulator for the HP 21xx and 1000 M/E/F-Series machines (hereafter referred collectively
as the HP computer family unless a specific machine reference is required). A large variety of CPU options, device
interface cards, and peripherals are provided.
This simulator does not model the 1000 L/A-Series machines. While these machines use the same base
instruction set, the I/O structure is entirely different, and the interfaces are not interchangeable with those of the
21xx/1000 machines. Moreover, the peripherals provided by this simulator are, with few exceptions, not supported
on the L/A-Series. An L/A-Series implementation would be almost a completely new simulator and therefore likely
would be best constructed as a separate project.
1.2 Simulator Files
The simulator sources are divided into a set of files for the Simulator Control Program and its support libraries, and
a set of files for the HP 21xx/1000 CPU and device simulations; the latter reside in a subdirectory of the directory
that contains the SCP files. The former set is common to all SIMH simulators, whereas the latter set is specific to
the virtual machine being simulated. The files that make up this simulator are:
