30
The trace formats are interpreted as follows:
>>DCPC1 cmd: Channel transfer completed
>>DCPC1 csrw: Control word 1 is STC | CLC | select code 23
>>DCPC1 sr: Select code 23 asserted SRQ
>>DCPC1 iobus: Received data 000000 with signals STC | CLF
Operational message
>>DCPC1 data: B 0002 05757 105736 dma write
Memory access classification
Octal data (memory contents)
Octal logical address (effective address)
Octal physical page number
Memory map (port A/port B/disabled)
Each DMA/DCPC channel state contains these registers:
Name
Size
Radix
Symbolic
Description
XFR
1
2
Channel is active
CTL
1
2
Channel interrupt is enabled
FLG
1
2
Channel is ready
FBF
1
2
Channel is ready (buffer)
CTL2
1
2
Command word 2/3 selector
CW1
16
8
Command word 1
CW2
16
8
Command word 2
CW3
16
8
Command word 3
BYTE
1
2
Even/odd byte-packing flag
PACKER
8
8
Byte-packing register
The BYTE and PACKER registers are applicable only to the 12578A controller. The PACKER register defaults to
single-character format display and entry but may be overridden with a numeric-format switch, if desired.
3.3 12581A/12892B Memory Protect
Memory protection is standard equipment on the 2100 (although it may be disabled by removing a jumper) and
optional on the 2116 and 1000. It provides a Fence Register whose setting divides the logical address space of the
CPU into protected and unprotected parts. When enabled, memory locations below the fence cannot be altered,
nor can execution jump to addresses below the fence. Violations cause the offending instruction to be aborted, the
address of the instruction to be recorded in the Violation Register, and an interrupt to select code 5. The 12892B
Memory Protect option for the 1000 has three feature options that are implemented by jumper settings. The default
configuration provides compatibility with 12581A Memory Protect option for the 2116 and the standard memory
protection for the 2100.
