System synchronization clock specifications
System synchronization clock specifications
10 MHz system reference clock: PXI_CLK10
10 MHz system reference clock: PXI_CLK10
Specification
Specification
Value
Value
Maximum slot-to-slot skew
1 ns
Accuracy
±25 ppm max (guaranteed over the operating
temperature range)
Maximum jitter
5 ps RMS phase jitter (10 Hz to 1 MHz range)
Duty factor
45% to 55%
Unloaded signal swing
3.3 V ±0.3 V
NOTE:
NOTE:
For other specifications, see 'PXI-1 Hardware Specification' at the PXI Systems Alliance website
(http://www.pxisa.org/userfiles/files/Specifications/PXIHWSPEC22.pdf
http://www.pxisa.org/userfiles/files/Specifications/PXIHWSPEC22.pdf).
100 MHz system reference clock:
100 MHz system reference clock: PXIe_CLK100 and PXIe_SYNC100
PXIe_CLK100 and PXIe_SYNC100
Specification
Specification
Value
Value
Maximum slot-to-slot skew
200 ps
Accuracy
±25 ppm max (guaranteed over the operating
temperature range)
Maximum jitter
5 ps RMS phase jitter (10 Hz to 12 kHz range); 5 ps RMS
phase jitter (12 kHz to 20 MHz range)
Duty factor for PXIe_CLK100
45% to 55%
Absolute single-ended voltage swing (when each line in
the differential pair has 50 W termination to 1.30 V or
Thévenin equivalent)
400 mV to 1,000 mV
NOTE:
NOTE:
For other specifications, see 'PXI-5 PXI Express Hardware Specification' at the PXI Systems Alliance website
(http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF
http://www.pxisa.org/userfiles/files/Specifications/PXIEXPRESS_HW_SPEC_R1.PDF).
External 10 MHz reference out (SMA on front panel of chassis)
External 10 MHz reference out (SMA on front panel of chassis)
Specification
Specification
Value
Value
Accuracy
±25 ppm max (guaranteed over the operating
temperature range)
Maximum jitter
5 ps RMS phase jitter (10 Hz to 1 MHz range)
Output amplitude
1 VPP ±20% square wave into 50
Ω
2 VPP unloaded
Output impedance
50
Ω
±5
Ω
External clock source
External clock source
Specification
Specification
Value
Value
Frequency
10 MHz ±100 PPM
Input amplitude
Input amplitude
—
System synchronization clock specifications
155
Summary of Contents for Edgeline EL1000
Page 1: ...HPE Edgeline EL1000 System User Guide Part Number 10 191019 Q321 Published May 2021 Edition 1 ...
Page 8: ...PCIe configuration PCIe configuration 8 ...
Page 13: ...PXI PXIe configuration PXI PXIe configuration 13 ...
Page 45: ...Setup Setup 45 ...
Page 52: ...Hardware options installation Hardware options installation 52 ...
Page 55: ...3 Install the system in the rack mount Installing the rack mounting option kit 55 ...
Page 64: ...Install the PXI PXIe card 64 ...
Page 69: ...9 Install the antenna Installing a full length mini PCIe LTE module 69 ...
Page 74: ...Configuration Configuration 74 ...
Page 76: ...Accessing the System Utilities menu 76 ...
Page 90: ...Software and configuration utilities Software and configuration utilities 90 ...
Page 119: ...Troubleshooting Troubleshooting 119 ...
Page 121: ...Battery Battery 121 ...
Page 124: ...Warranty and regulatory information Warranty and regulatory information 124 ...
Page 127: ...Japnese certification mark for WiFi module Japnese certification mark for WiFi module 127 ...
Page 128: ...Japanese certification mark for LTE module Japanese certification mark for LTE module 128 ...
Page 131: ...Ukraine RoHS material content declaration Ukraine RoHS material content declaration 131 ...
Page 137: ...Electrostatic discharge Electrostatic discharge 137 ...
Page 140: ...Specifications Specifications 140 ...
Page 157: ...Support and other resources Support and other resources 157 ...