HP 9000 V-Class, Operator'S Manual

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10 Chapter 1
Overview
Shared memory
Shared memory
V-Class servers provide exceptionally high performance using a shared-
memory architecture; it allows the developer, compilers, and applications
to view the system as a number of processors sharing a large physical
memory and a number of high-bandwidth I/O ports.
Message passing (Data Mover) hardware provides high performance for
applications developed using explicit MPI messaging.
Compilers use shared memory to provide automatic, efficient
parallelization while viewing memory as a single contiguous virtual
address space.
The Hyperplane crossbar provides high-bandwidth, low-latency
nonblocking access from processors and I/O channels to the system
memory. It prevents the performance drop-off associated with systems
that employ a system-wide bus for processor and I/O memory traffic.
Sequential memory references (linearly ascending physical address) to
shared memory are interleaved across up to eight memory boards on a
32-byte basis. See V-Class Architecture for information regarding
memory interleaving.
With all processor references to memory, copies of the accessed data are
encached into either the instruction or data caches of each processor. If
the processor making the memory reference modifies the data and if
another processor references that same data while a copy is still in the
first processor cache, a condition exists whereby the data has become
stale. The V-Class hardware continually works to ensure that the second
processor does not use an outdated copy of the data from memory. The
state that is achieved when both processors’ caches always have the
latest value for the data is called cache coherence.
To maintain updated coherent copies, V-Class servers operate under the
following rules:
Any number of read encachements of a cache line can be made at a single
time. The cache line can be read-shared in multiple caches.