HP 9000 V-Class, Operator'S Manual

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Chapter 1 3
Overview
The node
The node
The V-Class server can contain four to 16 processors. The terms node and
system are used interchangeably in this book. The node uses a
symmetric multiprocessor (SMP) design that can exploit fine-grain
parallelism.
A conceptual block diagram of the node is shown in Figure 1. Centrally
located in the diagram is the HP Hyperplane crossbar that is comprised
of four Exemplar Routing Attachment Controllers (ERAC). The
Hyperplane crossbar allows all of the processors to access all of the
available memory. Processors are installed on Exemplar Processor Agent
Controllers (EPACs). An EPAC allows the processor and the I/O
subsystem (the Exemplar PCI-bus Interface controller—EPIC) access to
the Hyperplane crossbar.
Also connected to the Hyperplane crossbar are the Exemplar Memory
Access controllers (EMAC). Up to two processors are located on each
EPAC. Memory is controlled by the EMAC. Input and output devices
connect to the node through EPIC which is connected to the processor
agents.
The Exemplar Core Utilities board (ECUB—commonly called the
Utilities board) in the node contains a section of hardware called the core
logic. It provides interrupts to all of the processors in the system through
the core logic bus which connects to each processor agent. The ECUB
attaches to the Exemplar Node Routing board (ENRB) centrally located
in the node.