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Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:(+86) 075583794354

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

IPIC

15.2

GPIO AC Timing Specifications

Table 50

provides the GPIO input and output AC timing specifications.

16 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

16.1

IPIC DC Electrical Characteristics

Table 51

provides the DC electrical characteristics for the external interrupt pins.

16.2

IPIC AC Timing Specifications

Table 52

provides the IPIC input and output AC timing specifications.

Table 50. GPIO Input AC Timing Specifications

Parameter

Symbol

Min Unit

GPIO inputs—minimum pulse width

PIWID

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external

synchronous logic. GPIO inputs must be valid for at least t

PIWID

ns to ensure proper operation.

Table 51. IPIC DC Electrical Characteristics

Parameter

Symbol

Condition

Min

Max

Unit

Notes

Input high voltage

—

2.0

+ 0.3

—

Input low voltage

—

–0.3

0.8

—

Input current

—

±5

—

Output low voltage

= 8.0 mA

—

0.5

Output low voltage

= 3.2 mA

—

0.4

Notes:

1. This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT.
2. IRQ_OUT and MCP_OUT are open-drain pins; thus V

is not relevant for those pins.

Table 52. IPIC Input AC Timing Specifications

Parameter

Symbol

Min Unit

IPIC inputs—minimum pulse width

PICWID

Notes:

1. Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external

synchronous logic. IPIC inputs must be valid for at least t

PICWID

ns to ensure proper operation in edge triggered mode.

51 / 87

Summary of Contents for MPC8349EA

Page 1: ...ated Host Processor Family Reference Manual To locate published errata or updates for this document refer to the MPC8349EA product summary page on our website as listed on the back cover of this docum...

Page 2: ...al units within the MPC8349EA Figure 1 MPC8349EA Block Diagram Major features of the device are as follows Embedded PowerPC e300 processor core operates at up to 667 MHz High performance superscalar p...

Page 3: ...I O for DDR1 1 8 V SSTL2 compatible I O for DDR2 Dual three speed 10 100 1000 Ethernet controllers TSECs Dual controllers designed to comply with IEEE 802 3 802 3u 820 3x 802 3z 802 3ac standards Ethe...

Page 4: ...gorithms Programmable field size up to 2048 bits Elliptic curve cryptography F2m and F p modes Programmable field size up to 511 bits Data encryption standard DES execution unit DEU DES and 3DES algor...

Page 5: ...speed 12 Mbps and low speed 1 5 Mbps operations Direct connection to a high speed device without an external hub External PHY with serial and low pin count ULPI interfaces Local bus controller LBC Mu...

Page 6: ...mote PCI masters Misaligned transfer capability Data chaining and direct mode Interrupt on completed segment and chain DUART Two 4 wire interfaces RxD TxD RTS CTS Programming model compatible with the...

Page 7: ...LVIN 0 3 to LVDD 0 3 V 4 5 Local bus DUART CLKIN system control and power management I2C and JTAG signals OVIN 0 3 to OVDD 0 3 V 3 5 PCI OVIN 0 3 to OVDD 0 3 V 6 Storage temperature range TSTG 55 to...

Page 8: ...DD Table 2 Recommended Operating Conditions Parameter Symbol Recommended Value Unit Notes Core supply voltage for 667 MHz core frequency VDD 1 3 V 60 mV V 1 Core supply voltage VDD 1 2 V 60 mV V 1 PLL...

Page 9: ...mates 2 2 Power Sequencing This section details the power sequencing considerations for the MPC8349EA 2 2 1 Power Up Sequencing MPC8349EA does not require the core supply voltage VDD and AVDD and I O...

Page 10: ...lies fully ramp up In the case where the core voltage is applied first the core voltage supply must rise to 90 of its nominal value before the I O supplies reach 0 7 V see Figure 4 Figure 4 Power Sequ...

Page 11: ...nd a Dhrystone benchmark application 6 Maximum power is based on a voltage of VDD 1 3 V worst case process a junction temperature of TJ 105 C and an artificial smoke test Table 5 MPC8349EA Typical I O...

Page 12: ...0 3 0 4 V CLKIN input current 0 V VIN OVDD IIN 10 A PCI_SYNC_IN input current 0 V VIN 0 5 V or OVDD 0 5 V VIN OVDD IIN 10 A PCI_SYNC_IN input current 0 5 V VIN OVDD 0 5 V IIN 50 A Table 7 CLKIN AC Ti...

Page 13: ...arameter Symbol Min Typical Max Unit Notes EC_GTX_CLK125 frequency tG125 125 MHz EC_GTX_CLK125 cycle time tG125 8 ns EC_GTX_CLK125 rise and fall time LVDD 2 5 V LVDD 3 3 V tG125R tG125F 0 75 1 0 ns 1...

Page 14: ...on output 16 tPCI_SYNC_IN 1 Input setup time for POR configuration signals CFG_RESET_SOURCE 0 2 and CFG_CLKIN_DIV with respect to negation of PORESET when the MPC8349EA is in PCI host mode 4 tCLKIN 2...

Page 15: ...lly Addressed by This Document for silicon revision level determination 6 1 DDR and DDR2 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM c...

Page 16: ...n Symbol Min Max Unit Notes Input output capacitance DQ DQS DQS CIO 6 8 pF 1 Delta input output capacitance DQ DQS DQS CDIO 0 5 pF 1 Note 1 This parameter is sampled GVDD 1 8 V 0 090 V f 1 MHz TA 25 C...

Page 17: ...DRAM when GVDD typ 2 5 V Table 15 DDR SDRAM Capacitance for GVDD typ 2 5 V Parameter Condition Symbol Min Max Unit Notes Input output capacitance DQ DQS CIO 6 8 pF 1 Delta input output capacitance DQ...

Page 18: ...ons At recommended operating conditions with GVDD of 1 8 or 2 5 V 5 Parameter Symbol Min Max Unit Notes Controller Skew for MDQS MDQ MECC MDM tCISKEW ps 1 2 400 MHz 600 600 3 333 MHz 750 750 266 MHz 7...

Page 19: ...1 Min Max Unit Notes ADDR CMD MODT output setup with respect to MCK tDDKHAS ns 3 400 MHz 1 95 333 MHz 2 40 266 MHz 3 15 200 MHz 4 20 ADDR CMD MODT output hold with respect to MCK tDDKHAX ns 3 400 MHz...

Page 20: ...3 ADDR CMD includes all DDR SDRAM output signals except MCK MCK MCS and MDQ MECC MDM MDQS For the ADDR CMD setup and hold specifications it is assumed that the clock control register is set to adjust...

Page 21: ...R bus Figure 8 DDR AC Test Load 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8349EA 7 1 DUART DC Electrical Characteristics Table 21 provide...

Page 22: ...terface RGMII and reduced ten bit interface RTBI signals except management data input output MDIO and management data clock MDC The MII GMII and TBI interfaces are defined for 3 3 V and the RGMII and...

Page 23: ...TBI and MII DC Electrical Characteristics Parameter Symbol Conditions Min Max Unit Supply voltage 3 3 V LVDD 2 2 97 3 63 V Output high voltage VOH IOH 4 0 mA LVDD Min 2 40 LVDD 0 3 V Output low volta...

Page 24: ...ications follow the pattern t first two letters of functional block signal state reference state for inputs and t first two letters of functional block reference state signal state for outputs For exa...

Page 25: ...II receive timing GR with respect to the time data input signals D reaching the valid state V relative to the tRX clock reference K going to the high state H or setup time Also tGRDXKL symbolizes GMII...

Page 26: ...tate for outputs For example tMTKHDX symbolizes MII transmit timing MT for the time tMTX clock reference K going high H until data outputs D are invalid X In general the clock reference symbol is base...

Page 27: ...state for inputs and t first two letters of functional block reference state signal state for outputs For example tMRDVKH symbolizes MII receive timing MR with respect to the time data input signals...

Page 28: ...tTTXF 1 0 ns Notes 1 The symbols for timing specifications follow the pattern of t first two letters of functional block signal state reference state for inputs and t first two letters of functional b...

Page 29: ...TR with respect to the time data input signals D reach the valid state V relative to the tTRX clock reference K going to the high H state or setup time Also tTRDXKH symbolizes TBI receive timing TR w...

Page 30: ...50 55 Duty cycle for 10BASE T and 100BASE TX3 5 tRGTH tRGT 40 50 60 Rise time 20 80 tRGTR 0 75 ns Fall time 80 20 tRGTF 0 75 ns Notes 1 In general the clock reference symbol for this section is based...

Page 31: ...I TBI and RTBI are specified in Section 8 1 Three Speed Ethernet Controller TSEC GMII MII TBI RGMII RTBI Electrical Characteristics 8 3 1 MII Management DC Electrical Characteristics The MDC and MDIO...

Page 32: ...in Max Unit Supply voltage 3 3 V LVDD 2 97 3 63 V Output high voltage VOH IOH 1 0 mA LVDD Min 2 10 LVDD 0 3 V Output low voltage VOL IOL 1 0 mA LVDD Min GND 0 50 V Input high voltage VIH 2 00 V Input...

Page 33: ...gh H until data outputs D are invalid X or data hold time Also tMDDVKH symbolizes management data timing MD with respect to the time data input signals D reach the valid state V relative to the tMDC c...

Page 34: ...Notes USB clock cycle time tUSCK 15 ns 2 5 Input setup to USB clock all inputs tUSIVKH 4 ns 2 5 Input hold to USB clock all inputs tUSIXKH 1 ns 2 5 USB clock to output valid all outputs tUSKHOV 7 ns 2...

Page 35: ...ignals 10 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8349EA 10 1 Local Bus DC Electrical Characteristics Table 37 provides the DC el...

Page 36: ...3 Output hold from local bus clock for LAD LDP tLBKHOX2 1 ns 3 Local bus clock to output high impedance for LAD LDP tLBKHOZ 3 8 ns 8 Notes 1 The symbols for timing specifications follow the pattern o...

Page 37: ...mple tLBIXKH1 symbolizes local bus timing LB for the input I to go invalid X with respect to the time the tLBK clock reference K goes high H in this case for clock one 1 Also tLBKHOX symbolizes local...

Page 38: ...Only DLL Enabled Figure 22 Local Bus Signals Nonspecial Signals Only DLL Bypass Mode Output Signals LA 27 31 LBCTL LBCKE LOE LSDA10 LSDWE LSDRAS LSDCAS LSDDQM 0 3 tLBKHOV tLBKHOV tLBKHOV LSYNC_IN Inpu...

Page 39: ...KDIV 2 DLL Enabled Figure 24 Local Bus Signals GPCM UPM Signals for LCCR CLKDIV 2 DLL Bypass Mode LSYNC_IN UPM Mode Input Signal LUPWAIT tLBIXKH2 tLBIVKH2 tLBIVKH1 tLBIXKH1 tLBKHOZ1 T1 T3 Input Signal...

Page 40: ...Integrated Host Processor Hardware Specifications Rev 13 40 Freescale Semiconductor Local Bus Figure 25 Local Bus Signals GPCM UPM Signals for LCCR CLKDIV 4 DLL Bypass Mode LCLK UPM Mode Input Signal...

Page 41: ...E Std 1149 1 JTAG interface of the MPC8349EA 11 1 JTAG DC Electrical Characteristics Table 40 provides the DC electrical characteristics for the IEEE Std 1149 1 JTAG interface of the MPC8349EA Table 4...

Page 42: ...age VOL IOL 3 2 mA 0 4 V Table 41 JTAG AC Timing Specifications Independent of CLKIN 1 At recommended operating conditions see Table 2 Parameter Symbol2 Min Max Unit Notes JTAG external clock frequenc...

Page 43: ...ttern of t first two letters of functional block signal state reference state for inputs and t first two letters of functional block reference state signal state for outputs For example tJTDVKH symbol...

Page 44: ...ndary scan timing diagram Figure 30 Boundary Scan Timing Diagram Figure 31 provides the test access port timing diagram Figure 31 Test Access Port Timing Diagram VM Midpoint Voltage OVDD 2 VM VM tJTDV...

Page 45: ...level VIL 0 3 0 3 OVDD V Low level output voltage VOL 0 0 2 OVDD V 1 Output fall time from VIH min to VIL max with a bus capacitance from 10 to 400 pF tI2KLKV 20 0 1 CB 250 ns 2 Pulse width of spikes...

Page 46: ...ing I2 with respect to the time data input signals D reach the valid state V relative to the tI2C clock reference K going to the high H state or setup time Also tI2SXKL symbolizes I2 C timing I2 for t...

Page 47: ...PCI input clock depending on whether the device is configured as a host or agent device Table 45 provides the PCI AC timing specifications at 66 MHz Table 44 PCI DC Electrical Characteristics Paramete...

Page 48: ...ge current specification 5 Input timings are measured at the pin 6 The setup and hold time is with respect to the rising edge of PORESET Table 46 PCI AC Timing Specifications at 33 MHz Parameter Symbo...

Page 49: ...Figure 36 shows the PCI output AC timing diagram Figure 36 PCI Output AC Timing Diagram 14 Timers This section describes the DC and AC electrical specifications for the timers 14 1 Timer DC Electrical...

Page 50: ...Timers Input AC Timing Specifications1 Parameter Symbol2 Min Unit Timers inputs minimum pulse width tTIWID 20 ns Notes 1 Input specifications are measured from the 50 percent level of the signal to th...

Page 51: ...the rising edge of CLKIN Timings are measured at the pin 2 GPIO inputs and outputs are asynchronous to any visible clock GPIO outputs should be synchronized before use by external synchronous logic GP...

Page 52: ...ications1 Parameter Symbol2 Min Max Unit SPI outputs valid Master mode internal clock delay tNIKHOV 6 ns SPI outputs hold Master mode internal clock delay tNIKHOX 0 5 ns SPI outputs valid Slave mode e...

Page 53: ...igure 38 shows the SPI timings in slave mode external clock Figure 38 SPI AC Timing in Slave Mode External Clock Diagram Figure 39 shows the SPI timings in master mode internal clock Figure 39 SPI AC...

Page 54: ...ssor Hardware Specifications Rev 13 54 Freescale Semiconductor Package and Pin Listings 18 1 Package Parameters for the MPC8349EA TBGA The package parameters are provided in the following list The pac...

Page 55: ...ensions for the MPC8349EA TBGA Figure 40 shows the mechanical dimensions and bottom surface nomenclature for the MPC8349EA 672 TBGA package Figure 40 Mechanical Dimensions and Bottom Surface Nomenclat...

Page 56: ...K34 L33 L34 P34 R29 R30 R33 R34 T31 T32 T33 U31 U34 V31 V32 V33 V34 W33 W34 I O OVDD PCI1_C BE 3 0 J30 M31 P33 T34 I O OVDD PCI1_PAR P32 I O OVDD PCI1_FRAME M32 I O OVDD 5 PCI1_TRDY N29 I O OVDD 5 PCI...

Page 57: ...M66EN A19 I OVDD DDR SDRAM Memory Interface MDQ 0 63 D5 A3 C3 D3 C4 B3 C2 D4 D2 E5 G2 H6 E4 F3 G4 G3 H1 J2 L6 M6 H2 K6 L2 M4 N2 P4 R2 T4 P6 P3 R1 T2 AB5 AA3 AD6 AE4 AB4 AC2 AD3 AE6 AE3 AG4 AK5 AK4 AE2...

Page 58: ...D LDP 1 CKSTOP_IN AP22 I O OVDD LDP 2 LCS 4 AN22 I O OVDD LDP 3 LCS 5 AM22 I O OVDD LA 27 31 AK21 AP23 AN23 AP24 AK22 O OVDD LCS 0 3 AN24 AL23 AP25 AN25 O OVDD LWE 0 3 LSDDQM 0 3 LBS 0 3 AK23 AP26 AL2...

Page 59: ...1_TGATE3 GTM2_TGATE4 D23 I O OVDD GPIO1 8 DMA_DDONE2 GTM1_TOUT3 B23 I O OVDD GPIO1 9 DMA_DREQ3 GTM1_TIN4 GTM2_TIN3 A23 I O OVDD GPIO1 10 DMA_DACK3 GTM1_TGATE4 GTM2_TGATE3 F22 I O OVDD GPIO1 11 DMA_DDO...

Page 60: ...11_DMMD B30 I O OVDD MPH0_D4_DP DR_D12_VBUS_VLD C30 I O OVDD MPH0_D5_DM DR_D13_SESS_END A31 I O OVDD MPH0_D6_SER_RCV DR_D14 B31 I O OVDD MPH0_D7_DRVVBUS DR_D15_IDPULLUP C31 I O OVDD MPH0_NXT DR_RX_ACT...

Page 61: ...O OVDD TSEC1_RXD 3 0 E10 A8 F10 B8 I LVDD1 TSEC1_TX_CLK D17 I OVDD TSEC1_TXD 7 4 GPIO2 27 30 A15 B15 A14 B14 I O OVDD TSEC1_TXD 3 0 A10 E11 B10 A9 O LVDD1 10 TSEC1_TX_EN B9 O LVDD1 TSEC1_TX_ER GPIO2 3...

Page 62: ...28 AM29 I O OVDD UART_CTS 1 MSRCID4 LSRCID4 AP30 I O OVDD UART_CTS 2 MDVAL LDVAL AN30 I O OVDD UART_RTS 1 2 AP31 AM30 O OVDD I2C interface IIC1_SDA AK29 I O OVDD 2 IIC1_SCL AP32 I O OVDD 2 IIC2_SDA AN...

Page 63: ...4 Test TEST D22 I OVDD 6 TEST_SEL AL13 I OVDD 6 PMC QUIESCE A18 O OVDD System Control PORESET C18 I OVDD HRESET B18 I O OVDD 1 SRESET D18 I O OVDD 2 Thermal Management THERM0 K32 I 8 Power and Ground...

Page 64: ...J5 K4 K5 L4 N4 P5 R6 T6 U5 V1 W5 Y5 AA4 AB3 AC4 AD5 AF3 AG5 AH2 AH5 AH6 AJ6 AK6 AK8 AK9 AL6 Power for DDR DRAM I O voltage 2 5 V GVDD LVDD1 C9 D11 Power for three speed Ethernet 1 and for Ethernet ma...

Page 65: ...ull up P FETs that are always enabled 5 This pin should have a weak pull up if the chip is in PCI host mode Follow the PCI specifications 6 This pin must always be tied to GND 7 This pin must always b...

Page 66: ...ration input selects whether CLKIN or CLKIN 2 is driven out on the PCI_SYNC_OUT signal The OCCR PCICDn parameters select whether CLKIN or CLKIN 2 is driven out on the PCI_CLK_OUTn signals PCI_SYNC_OUT...

Page 67: ...the chapter on reset clocking and initialization in the MPC8349EA Reference Manual for more information on the clock subsystem The internal ddr_clk frequency is determined by the following equation d...

Page 68: ...2 and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies The value of SCCR ENCCM SCCR USBDRCM and SCCR USBMPHCM must be programmed so that the maximum interna...

Page 69: ...select the ratio between the primary clock input CLKIN or PCI_CLK and the internal coherent system bus clock csb_clk Table 59 and Table 60 show the expected frequency values for the CSB frequency for...

Page 70: ...Low 0000 16 1 266 High 0010 2 1 133 High 0011 3 1 100 200 High 0100 4 1 133 266 High 0101 5 1 166 333 High 0110 6 1 200 High 0111 7 1 233 High 1000 8 1 1 CFG_CLKIN_DIV selects the ratio between CLKIN...

Page 71: ...O divider VCO divider must be set properly so that the core VCO frequency is in the range of 800 1800 MHz Low 0110 6 1 100 150 200 Low 0111 7 1 116 175 233 Low 1000 8 1 133 200 266 Low 1001 9 1 150 22...

Page 72: ...ore VCO frequency core frequency VCO divider The VCO divider must be set properly so that the core VCO frequency is in the range of 800 1800 MHz 0 1 2 5 6 nn 0000 n PLL bypassed PLL off csb_clk clocks...

Page 73: ...011 33 233 350 33 233 350 33 233 350 604 0110 0000100 33 200 400 33 200 400 33 200 400 624 0110 0100100 33 200 400 33 200 400 33 200 400 803 1000 0000011 33 266 400 33 266 400 33 266 400 823 1000 0100...

Page 74: ...input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode Table 63 Package Thermal Characteristics for TBGA Characteristic Symbol Value Unit Notes Junction to ambient natural convection on...

Page 75: ...e with Junction to Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance The thermal performance of any component...

Page 76: ...ion of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available use the thermal characterization parameter JT to determine the junctio...

Page 77: ...not a standard application environment a standard heat sink is not required Table 64 shows heat sink thermal resistance for TBGA of the MPC8349EA Accurate thermal design requires thermal modeling of t...

Page 78: ...esearch Corporation IERC 818 842 7277 413 North Moss St Burbank CA 91502 Internet www ctscorp com Millennium Electronics MEI 408 436 8770 Loroco Sites 671 East Brokaw Road San Jose CA 95112 Internet w...

Page 79: ...ction Temperature with a Heat Sink When a heat sink is used the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface mater...

Page 80: ...s of equal value are recommended over a single large value capacitor To minimize noise coupled from nearby circuits each circuit should be placed as closely as possible to the specific AVDD pin being...

Page 81: ...DC Impedance The MPC8349EA drivers are characterized over process voltage and temperature For all buses the driver is a push pull single ended driver type open drain for I2 C To measure Z0 for the sin...

Page 82: ...ed with the large value of the pull up pull down resistor should minimize the disruption of signal quality or speed for the output pins 21 7 Pull Up Resistor Requirements The MPC8349EA requires high r...

Page 83: ...clature MPC nnnn e t pp aa a r Product Code Part Identifier Encryption Acceleration Temperature1 Range Package2 Processor Frequency3 Platform Frequency Revision Level MPC 8349 Blank Not included E inc...

Page 84: ...29 and Table 31 removed the GTX_CLK125 In Table 34 updated tMDKHDX Max value from 170ns to 70ns 12 11 2010 In Table 55 added note for pin LGPL4 In Section 21 7 Pull Up Resistor Requirements updated t...

Page 85: ...57 Operating Frequencies for TBGA in the Coherent system bus frequency csb_clk row changed the value in the 533 MHz column to 100 333 In Table 63 Suggested PLL Configurations under the subhead 33 MHz...

Page 86: ...h level input voltage values to min 2 and max OVDD 0 3 changed low level input voltage values to min 0 3 and max 0 8 Updated DDR2 I O power values in Table 5 MPC8347EA Typical I O Power Dissipation In...

Page 87: ...ath may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers...

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