Hotenda MPC8349EA, Technical Data Manual

Page: 48 / 87

Electronic Component Distributor. Source::Freescale Semiconductor
P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
48 Freescale Semiconductor
PCI
Table 46 provides the PCI AC timing specifications at 33 MHz.
PORESET to REQ64 hold time t
PCRHRX
0 50 ns 6
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.
2. The symbols for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for inputs
and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
PCIVKH
symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
SYS
, reference (K) going
to the high (H) state or setup time. Also, t
PCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications .
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The setup and hold time is with respect to the rising edge of PORESET.
Table 46. PCI AC Timing Specifications at 33 MHz
Parameter Symbol
1
Min Max Unit Notes
Clock to output valid t
PCKHOV
— 11 ns 2
Output hold from clock t
PCKHOX
2 — ns 2
Clock to output high impedance t
PCKHOZ
— 14 ns 2, 3
Input setup to clock t
PCIVKH
3.0 — ns 2, 4
Input hold from clock t
PCIXKH
0 — ns 2, 4
REQ64 to PORESET setup time t
PCRVRH
5 — clocks 5
PORESET to REQ64 hold time t
PCRHRX
0 50 ns 5
Notes:
1. The symbols for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for inputs
and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
PCIVKH
symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
SYS
, reference (K) going
to the high (H) state or setup time. Also, t
PCRHFV
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications .
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The setup and hold time is with respect to the rising edge of PORESET.
Table 45. PCI AC Timing Specifications at 66 MHz
1
(continued)
Parameter Symbol
2
Min Max Unit Notes
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