Hotenda MPC8349EA, Technical Data Manual

Page: 26 / 87

Electronic Component Distributor. Source::Freescale Semiconductor
P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:sales@hotenda.cn Phone:(+86) 075583794354
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
26 Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 11 shows the MII transmit AC timing diagram.
Figure 11. MII Transmit AC Timing Diagram
8.2.2.2 MII Receive AC Timing Specifications
Table 28 provides the MII receive AC timing specifications.
TX_CLK data clock rise (20%–80%) t
MTXR
1.0 — 4.0 ns
TX_CLK data clock fall (80%–20%) t
MTXF
1.0 — 4.0 ns
Note:
1. The symbols for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for inputs
and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
MTKHDX
symbolizes MII transmit timing
(MT) for the time t
MTX
clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference
symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of t
MTX
represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
Table 28. MII Receive AC Timing Specifications
At recommended operating conditions with LV
DD
/OV
DD
of 3.3 V ± 10%.
Parameter/Condition Symbol
1
Min Typ Max Unit
RX_CLK clock period 10 Mbps t
MRX
— 400 — ns
RX_CLK clock period 100 Mbps t
MRX
— 40 — ns
RX_CLK duty cycle t
MRXH
/t
MRX
35 — 65 %
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK t
MRDVKH
10.0 — — ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK t
MRDXKH
10.0 — — ns
Table 27. MII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LV
DD
/OV
DD
of 3.3 V ± 10%.
Parameter/Condition Symbol
1
Min Typ Max Unit
TX_CLK
TXD[3:0]
t
MTKHDX
t
MTX
t
MTXH
t
MTXR
t
MTXF
TX_EN
TX_ER
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