Holtek HT46R22, Handbook

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Programmable Frequency Divider
-
PFD
The PFD output is pin-shared with the I/O pin PA3. The function is selected via configuration op-
tion, however, if not selected, the pin can operate as a normal I/O pin. Note that for the HT46R24/
HT46C24 devices, which have two internal timers, the timer source for the PFD can be chosen, via
configuration option, to come from either one of the two timers.
The timer overflow signal is the clock source for the PFD circuit. The output frequency is controlled
by loading the required values into the timer prescaler registers to give the required division ratio.
The counter, driven by the system clock which is divided by the prescaler value, will begin to
count-up from this preload register value until full, at which point an overflow signal is generated,
causing the PFD output to change state. The counter will then be automatically reloaded with the
preload register value and continue counting-up. Refer to the relevant Timer/Event Counters sec-
tion for details of its settings and operations.
For the PFD output to function, it is essential that the corresponding bit of the Port A control regis-
ter PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however,
the pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set
to
²
1
²
. This output data bit is used as the on/off control bit for the PFD output. Note that the PFD
output will be low if the PA3 output data bit is cleared to
²
0
²
.
Using this method of frequency generation, and if a crystal oscillator is used for the system clock,
very precise values of frequency can be generated.
Chapter 1 Hardware Structure
41
T i m e r O v e r f l o w
P F D C l o c k
P A 3 D a t a
P F D O u t p u t a t P A 3
+ 1 + 2 + 3 + 4
T i m e r
E x t e r n a l T i m e r
P i n I n p u t
T O N , T 0 O N o r T 1 O N
( w i t h T E , T 0 E o r T 1 E = 0 )
P r e s c a l e r O u t p u t
( w i t h c l o c k = f
S Y S
)
I n c r e m e n t
T i m e r C o u n t e r
P r e s c a l e r O u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .
Pulse Width Measurement Mode Timing Chart