Holtek HT46R22, Handbook

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System Architecture
A key factor in the high performance features of the Holtek range of A/D Type microcontrollers is at-
tributed to the internal system architecture. The range of devices take advantage of the usual fea-
tures found within RISC microcontrollers providing increased speed of operation and enhanced
performance. The pipelining scheme is implemented in such a way that instruction fetching and in-
struction execution are overlapped, hence instructions are effectively executed in one cycle, with
the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations
of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, dec-
rement, branch decisions, etc. The internal data path is simplified by moving data through the Ac-
cumulator and the ALU. Certain internal registers are implemented in the Data Memory and can
be directly or indirectly addressed. The simple addressing methods of these registers along with
additional architectural features ensure that a minimum of external components is required to pro-
vide a functional I/O and A/D control system with maximum reliability and flexibility. This makes
these devices suitable for low cost, high-volume production for controller applications requiring
from 2K up to 8K words of program memory and from 64 to 384 bytes of data storage.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecu-
tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the con-
tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the in-
struction will take one more instruction cycle to execute.
Note When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This
T1 phase clock has a frequency of f
SYS
/4 with a 1:3 high/low duty cycle.
Chapter 1 Hardware Structure
15
F e t c h I n s t . ( P C )
E x e c u t e I n s t . ( P C - 1 )
F e t c h I n s t . ( P C + 1 )
E x e c u t e I n s t . ( P C )
F e t c h I n s t . ( P C + 2 )
E x e c u t e I n s t . ( P C + 1 )
P C P C + 1 P C + 2
O s c i l l a t o r C l o c k
( S y s t e m C l o c k )
P h a s e C l o c k T 1
P r o g r a m C o u n t e r
P h a s e C l o c k T 2
P h a s e C l o c k T 3
P h a s e C l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining