Rev. 1.20
86
October 28, 2020
BC45B4523
Power Supply & Grounding
In NFC systems, the receiver extracts the card-response signal from the envelope of the RF carrier on the antenna.
Except for some smartcards where their operating range is deliberately limited by their designs, the noise in
transmitter, which inevitably reflects back to receiver system, is a limiting factor for the reading performance,
especially in ISO15693. The noise in the transmitter is mainly stemmed from the transmitter power supply ripple
and clock jitter. The clock jitter is from the analog power supply noise, in which the oscillator relies on, and the
cleanliness of the clock source.
To achieve the highest reading performance, the noise in both transmitter and receiver parts should be as low
as possible. The noise in the receiver is fundamentally limited to electronic noise as stated in the “Reveiver
Characteristics”. Therefore, common techniques, such as power supply separation, decoupling capacitor and
grounding, should be employed. The device provides three power-supply sets for a transmitter, an analog part and
a digital input/output part. Positive power supply of each part can be simply separated by ferrite beads. A more
effective measure is to use dedicated regulators to block the noise feeding through other parts. Local decoupling
capacitors, 10μF tantalum and 0.1μF ceramic, must be provided to supply high-frequency current and placed close
to each power supply input. In floor-planning, external high-current sections, unrelated to RF transmission and
noise-generating components, must be grouped and placed far away from sensitive analog parts such as oscillator,
external envelope detector and RF transmitter. For example, the high current component can be a switching power
supply, while the noise generating component can be a microcontroller or host interface components. For NFC
reader applications, the analog ground A_VSS and the transmitter ground T_VSS must be on the same ground to
keep the same potential for both the receiver and the transmitter. Physically, the analog and transmitter ground can
be connected by a unified solid ground plane. As typical technique used in mixed-signal system, the analog part
and the digital part, digital section of the device and the external microcontroller, can be on the same ground plane.
However, the power source direction and the ground return path from such noisy components should be carefully
designed to avoid current superimposition causing a bouncing between the analog and the transmitter ground. A
switching power supply and a heavy driver for the interface must be placed on the isolated ground plane with the
isolated return path. In case of the switching power supply, the operating frequency must carefully be designed so
that it is not overlap the operating bandwidth. Magnetic shield inductor and component selection can be employed
to reduce such effect.
Test Signals
The device internal signal can be probed out via TA and TD pins for multiples purpose. These pins are applied for
monitoring and debugging signal for both Manchester and BPSK pattern. Furthermore, they can be fed to external
MCU to decode other protocols which the device does not support.
For Manchester-and-FSK decoder in ISO14443A and ISO15693, the purpose of test signal is for monitoring and
fine-tuning the time wait, Twait, between EOF of the transmitted data and SOF of the received data. The Twait,
defined by BitPhase and RxWait registers, must be synchronously set to make the decoder evaluate correctly.
The following “OUT3P and RESET_INT” figure shows internal signals during Manchester-coding reception
in ISO14443A, RESET_INT used in resetting evaluation results of each half bit and input analog signal, and
OUT3P is for the Manchester-and-FSK decoder. Also, the OUT3P is the amplifed envelope from the last state
amplifier. Active state of RESET_INT, indicating point in resetting for each half bit, must be set to coincide with
the beginning point the Manchester-and-FSK-decoder input signal burst, OUT3P. By adjusting registers BitPhase
and RxWait, the proper alignment of OUT3P and RESET_INT as shown in the figure can be achieved. Note that
the period of RESET_INT is equal to half ETU of the operating standard. This results in a complete integration
of each half bit, VRECT, as shown in the other three figures below, which display the evaluation result CORR_
S_VALID, CORR_S_DATA and CORR_S_COLL respectively. CORR_S_VALID shows the validity of data
evaluation, CORR_S_DATA displays the evaluation result while CORR_S_COLL expresses the collision result of
data stream.