Rev. 1.20
2
October 28, 2020
BC45B4523
amplitudes as low as 1mV
pp
without distorting the data
integrity. The receiver filters can be selected optionally
either to a predefined band in accordance with the
generic required standard setup, or to an arbitrarily
defined combination which gives flexibility to cope with
various antenna variations/parameters. The baseband
circuits permit the inbound/outbound configuration to
accept various forms of customized protocols, incoming
to the chip and outgoing to the external RF circuitry in
the application specific-design system.
The transmitter is capable of accepting a wide range of
operating supply voltages to serve various applications,
e.g., 5V for base stations or desktop readers, and 3.3V
for handheld devices. The transmission controller
is entirely used to support all operation status and
requests, including FIFO status full/high/low and
transmission complete flag. The transmitter drivers
support a wide range of power supply voltages from
2.7V to 5.5V. A high drive current up to 250mA is
guaranteed for demanding item-level mid-range reader
designs. The dual high-powered transmitters can be
flexibly configured in various configurations, e.g.
differential driving, single-ended driving and a mode
to drive an external Class-E amplifier for improving
the drive strength in the gate antenna setup.
The BC45B4523 contains efficient power saving
modes: Hard Power Down, Soft Power Down,
Standby and low-power Card Detection modes. The
low-power Card Detection mode allows the device
to not operate at full power continuously. The device
periodically detects external card. If an external card
is detected, interrupt signal will be sent to MCU to
wake up the system.
To facilitate operation of the companion microcontroller,
the BC45B4523 is fully equipped with on-chip
peripheral support devices such as an RF-trig timer,
a host interrupt generator and a clock divider. The
BC45B4523 is offered in a QFN package with excellent
heat dissipation when self-mounted on PCB.
Block Diagram
Bit Level CODEC
Encryption
Engine
Frame CODEC
State Machine /
Wake Up Controller /
Flow Control
CRC
Generator
WkUp
Timer
Program Timer
Power Mode
Control
Interface
Control ( SPI )
Registers
IRQ Controller
POR
MISO
MOSI
NCS
SCLK
IRQ
RSTPD
TD
DIG
I/O
FIFO
Transmitter
TX1
TX2
T_VSS
T_VDD
Data
Evaluator
Amp
ENV
RF
Amplitude
Detector
Voltage
Reference
IO_VDD
D_VDD
VREG_OUT
VREG_IN
XTAL1 XTAL2
Regulator
1V6
Regulator
3V3
RX
VMID
TA
CLK13M
A_VDD A_VSS
Receiver
Digital
D_VSS
Low Freq.
OSC
CLK16k
Functional Block Diagram