Rev. 1.20
70
October 28, 2020
BC45B4523
register sets all interrupt enable bits. The InterruptFlag is usually set by the internal state machine and cleared by
the external microcontroller, while InterruptEnable is always set and cleared by the external microcontroller.
Interrupt Flag
Indication when Interrupt is Set
Suggested Action for
Microcontroller
CDIRq
In Card Detection operation, both direct command or WkUpCD
mode
ADC_Result > CDThreshold_H or ADC_Result < CDThreshold_L
Begin to start RF communication
TimerIRq
General Timer (13.56MHz) decreases from 1 to 0 or set-up time
is up
Investigate cause of time out
Wake Up Timer (16.38kHz) underflow counter is decreased to 0
TxIRq
One of these events in these commands occurs
- Transmit: All data have been transmitted
- Transceive: All data have been transmitted
Start Receive command or start
other commands
One of these events in these commands occurs:
- RxFilterTune: Tuning process is finished
- CalCRC: All data have been processed
Begin to start other commands
One of these events in these commands occurs:
- LoadKeyFIFO: Key is already in buffer
Start Authent command
RxIRq
Receiver finishes reception in both cases of successful and error
Read Data from the FIFO
Investigate received data and
process for the next transmission
In Field Detection operation, both direct command or WkUpCD
mode
ADC_Result > FDThreshold_H
Turn off RF to avoid RF collision
IdleIRq
Operation of command is finished and state is changed to idle.
End of operation of all commands causes IdleIRq set to 1.
Setting power down or standby during executing or starting Idle
command does not set IdleIRq.
Begin to start other commands
HiAlertIRq
The FIFO is getting full and FIFOLength ≥ 64 - WaterLevel
Read Data from the FIFO to
prevent the FIFO Full
LoAlertIRq
The FIFO is getting empty and FIFOLength ≤ WaterLevel
Write Data to the FIFO if need
Source of Interrupt Trigger and Suggested Action for Microcontroller
Crypto_M Engine
The device incorporates a Crypto_M engine to encrypt the transmitted data and decrypt the received data. A
diagram of transmission and reception systems with a crypto engine is shown below. Before processing encryption
and decryption in read/write operations from/to Crypto_M card, the 48-bit keys of the data section being accessed
in the card must be previously loaded to the key buffer and the authentication process must be successful. The
following block diagram shows inter-block activities for commands associated with key loading. Bit Crypto_MOn
(Sector0-0x09.3) indicates the completion of the authentication process. This Crypto engine is only applicable for
transactions in ISO14443A at 106kbps.
Command
FIFO
Crypto Engine
Stream-in Data
Stream-out Data
Encrypted
stream-out Data
Encrypted
stream-in Data
Key Buffer
SPI
Inter-
face
Frame Decoder
LoadKeyFIFO
Bit Decoder
Signal
Diagram of Transmission and Reception Systems with a Crypto Engine