In
this
case,
RAM
used
the
page
mode
(other
display
address
can
be
accessed)
for
display,
l
piece
of
the
so
ifit
is
regarded
as
the
same
low
address
by
changing
column
address.
In
40
character
mode
display
address
per
1
MPU
clock
cycle
is
enough,
one
column
address
by
equaling
the
2
continuous
column
address
the
same.
CAS
signal
output
address
of
the
each
RAM
is
described
in
table
6-lO.
6-5-2
Colour
RAM
circuit
Semi
colour
graphic
method
is
in
use
to
display
colour
in
Basic
Master
Level
This
requires
to
read
the
characters
graphic
data
and
colour
information
at
the
same
time.
For
this
reason,
besides
32K
Byte
Standard
program
store
RAM,
the
system
has
another
5bit
x
16K
Byte
colour
RAM.
Fig
6-ll,
Fig
6~l2
shows
the
combination
of
the
displayed
colour
and
the
meaning
of
colour
RAM
5
bit.
By
this
RAM
5
bit,
the
colour
and
reverse
of
one
character
unit,
vertical
direction
1/8
character
unit
and
graphic/character
can
be
spe-
cified.
In
Level-3,
bi-directional
colourregisters
method
is
adopted
because
of
the
read/write
of
different
parts
of
the
memory
is
required.
The
general
concept
is
as
per
fig.
6-20.
The
and
I/O
colour
register
is
bi-directional
three
state
output
latch
capable
read
write
to
MPU,
and
used
for
read/write
from
MPU
to
colour
RAM
through
direction
each
one
piece
of
three
state
buffer
(IC78,
79,
HD74LS367AP).
The
RAM
common
address
are
allocated
for
store
RAM
and
colour
RAM,
but
colour
becomes
valid
only
when
the
registers
access
the
display
area
in
store
RAM.
Following
is
the
general
explanation
of
the
operation.
(1)
Display
Period
Display
data
is
sent
through
data
bus
to
video
signal
generator
from
store
RAM
and
colour
RAM.
(2)
M P U RAM
connect
period
when
MPU
read
the
display
area,
the
content
of
the
store
RAM
is
taken
into
bus
then
address
data
which
correspond
to
the
colour
RAM
is
colour
register.
MPU
via
data
taken
to
the
If
MPU
write
RAM.
At
the
colour
RAM.
the
data
display
area,
the
data
of
MPU
is
written
into
store
same
time,
the
content
of
the
colour
register
is
written
in
(3)
Colour
register
Mask
Bit
When
program
is
stored
store
RAM
of
display
RAM
area,
it
is
judged
by
one
bit
mask
ROM
of
the
colour
register
if
the
content
is
store
RAM
or
display
data
or
program.
By
this
method,
the
content
of
colour
register
will
not
be
destroyed
if
MPU
read
the
command.
If
recording
is
done
with
"H"
level
of
mask
bit,
the
content
in
colour
register
is
kept
even
ifstore
RAM
is
read.
In
case
of"L"
level,
colour
information
of
the
address
is
taken
into
colour
register
by
MPU
read
operation.
3
Summary of Contents for MB-6890
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