Hitachi MB-6890, Service Manual

Page: 59 / 123

Pig. .642
Colour
bit
combination of Displayed colour
’go
e
bit
2
bit l bit
0
kolou
9
0
0
0
Flack
1
6
o
1
blue
2
\
o 1
o
ed’
3
0
1
7
1
aqen a
4
1
C
0
0
rØen
5
|
1
0
1
an
6
1
1 1
0
ello
y
7
1
il
1
white!
Fig.
94|
Colour
Ram
5 Bit meanin
_
bit
4
bit
3
.
bitz
bitl
biifo
’H’
Graphi revere
r?6§
‹ d 3 N
IUQN
.L-
Chara.
Norma
~
edOFF
1d@FF
RAM¢ir¢
’t
xcssc]
xcsv
y
:ces
16355
ICS4
6-5
Ram
Block
6-5~l Operation
of
RAM
block
The
access
method of the
RAM
block
in Basic
Master
Level-3 is described
in
fig.
6-19.
In
this
system,
the address bus
between
RAM
and M U is connected
during
E
period
as
MPU-RAM
connection
period,
and in other period.
display
address bus between RAM and CRTC
is connected
as
display period.
The bus
change
is
done by MPU display
address
switch
signal (MPU DISP-SW
signal).
The
RAMS
(HM47l6AP-1)
in
use
in this
system
is addressing input 7
bit
Dynamic
RAM.
To
use
this
chip
as
equivalent
as
address input
l4bit
(l6KB)
Ram,
input of
l4bit
inputs
should be
separated to
7bit
low address
and 7bits
column address.
Each address should be inputted from
7
address
pin
by
time
sharing.
The Low address
is
taken by RAS signal,
so
does
column address
by CAS
signal.
RAS signal also act
as
Low address column
address SWitChi.T signal.
To display
80
character
mode in this
system,
2 continuous display address
must
be
read
during IMPU clock cycle. To
do
so,
MPU DISP-SW signal has display
period duty rate of about
the double of the MPU RAM
connection
period.
:r-r