Hitachi MB-6890 Service Manual Download Page 65 | Manualshive

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background image

signals.

In

this

conversion

period,

shift/Load

signals

are

inputted

to

ICll7

15

pin

which

makes

it

possible

to

output

video

signal

during

display

period.

(2)

Data

bit

from

colour

RAM

makes

the

timing

per

each

l

character

at

1c115

9

pin

input

(LOAD

signal)to

synchronize

with

brightness

signal

which

was

derived

from

ICll7.

(3)

The

brightness

signal

is

combined

with

display

reverse

signal

(REV

signal)

from

colour

RAM

at

ICl36

then

combined

with

cursor

display

signal

(CUR

DISP

signal

at

ICl3l.

I

(4)

To

make

the

synchronization

with

this

brightness

signal

and

colour

inform-

ation

signal

from

colour

RAM,

timing

is

set

per

each

l

dot

at

input

6

pin

(DOT

CK

signal)

of

ICll6.

Then,

after

switching

of

background

colour

signal

(R~BK,

G-BK,

B-BK)

of

ICll8

and

colour

signal

(R,

G,

B)

of

colour

RAM

to

brightness_signal

at

l

pin

input,

output

of

G

signal

to

4

pin,

R

signal

to

7

pin

and

B

signal

to

9

pin

of

ICll8

are

done.

After

reverse

buffering

these

signals

in

ICl32,

colour

display

colour

raw

signals

R,

G,

B

are

outputted

to

colour

display

connector;

(5)

R,

G,

B

signals

are

composed

with

synchronous

signal,

which

are

made

from

ICl32

and

ICl35,

at;/A

converter

then,

after

impedance

conversion

Q5,

these

signals

are

outputted

to

mono-chrome

video

terminal.

(6)

On

the

hand,

synchronous

signal

is

counted

by

synchronizing

the

E

(1,008

MHzl

signal

from

MPU

and

H

SYNC

signal

from

CRTC

in

ICl34,

ICl35,

then

out-

putted

to

IC96

pin

3

as

pulse

width

=

4ps

horizontal

synchronous

signal.

,,-

2 D i 1 - i § ’ 1

/,,-

aDiv-.LSQH

@@M@Q5M@

§§

amlllllls

DD,

lllllllll

’f------’

Hlllllll

m

Ill-I-I-I

WEBER

(0

Normal

Mode

(M

High

Resolution

Mode

sis

l

character

area

(correspondence

between

graphic

mode

and

data

bit)

Fig.643

The

Relationship

between

display

mode

and

graphic

resolution

Display

Mode

Graphic

ir

Display

_

"

’

’

RAM

Graphic

Mode

@g§§§gQ§§Ø

resolutlc

Capacity

40

80x

100

Normal

ch

H

v

I

1000Byte

90ch

I

H

160><

V100

zoooayte

40

h

H

320><

vzoo

3000

High

Resoluti

C

I

Byte

Boch

I

H

e4o><

Vzoo

15000Byte

A

A

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1

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«
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63
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65
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»

Summary of Contents for MB-6890

Page 1: ...HITACHI PERSONAL COMPUTER MB 6890 SERVICE MANUAL I R 0 3012 98 ...

Page 2: ...HITACHI PERSONAL COMPUTER MB 6890 SERVICE MANUAL ev O 30 1 2 1 ...

Page 3: ...fication 1 2 The name of each block 6 Function of I C s used 3 10 Explanation of the circuit Memory map Q iii i 31 Adjustment 82 Service points 85 The usage of inbuilt switches 87 Trouble shootings 91 Operation check method 102 Basic circuit diagram Basic P C B layout Waveform of each block Parts list 1 ...

Page 4: ...ette tape recorder printer and Light pen is attached as standard Built in interface connectors for future system expansion 3 Specification 3 1 General specification iIC Wl43pcs CPU 4pcs Power unit Transistor 7pcs CPU 8pcs Power unit p Diode lOpcs CPU 25pcs Power unit Speaker output O 4W _Speaker 6 x 9 cm l6 ohm _ l pcs I Input Output Cassette tape recorder connector CASSETTE Light pen connector L ...

Page 5: ...n pin Signal direction CPU Out NO NO CPU Out 7675 1 2 f137 vV _ 5V 3 4 LP VCMP 1 GND 5 3 Colour displav COLOR direction pin pin direction CPU out Slgnal No No Signal CPU out I2V 1 2 GND T 13 TT 3 4 QW T565 5 6 R G 1 s B 4 Rs 232C Int rfacems 232c direction _ pin pin direction CPU out Signal No No Signal CPU out 1 2 TxD RxD 3 4 RTS CTS s e i r GND 7 8 DCD 9 10 n 4 1 11 g 12 13 14 15 16 17 18 19 20 ...

Page 6: ...irecticn CPU _ QU_tI_ RAM4 RAM3 NO_ QO_ _ RAM3 RA114 _ CPU wut 12v Q 12v 1 QQ 2 GND Q GND _ sv Q sv 3 4 sv Q sv D0 Q D0 5 Q e D DQ Q D Q D 7 3 Q D1 D Q D Q D 9 10 Q D D D D 11 QQ 12 Q D D Q A R Q ARD 13 Q 14 Q AR AR AR Q AR Q15 16 Q AR AR AR Q AR _ I7 LE 18 1 AR AR _ V AR 3 AR 19 Q20 Q mis RAS CASQHZ CAS 52 21 22 Q 1 E1 WEE Q 2 _ ROSFKIL f R 0 1 1 1 i E 23 z 24 QRuw 0UT ww DUTQ s _ ___ 1 1 g D s E...

Page 7: ...10 D A 11 12 A 1 A A A Q13 Q14 A A 15 16 A A 17 18 A 4 A 19 20 A A 21 A 22 A A 23 24 A A 25 26 A _ BA 27 28 BS E555 29 so EXROM KIL 11 w IN 31 32 E356 R w OUT 33 A 34 VMA our 1 as as Q 1 1 37 38 FH T55 as 40 mi EXE4142WTTEE EXE 41 42 WTTEE ETA 43 44 XN 1FSW HALT ACK 45 46 SOUND IN ISMCK 47 48 GND f 2Mc1 49 so GND 1 5V 51 52 ffR 1 12v 53 54 12V GND 55 56 5v 5 ...

Page 8: ... msn asssr WN MIX POWER VOLUME MODE RESET Powaaon display light l Power switch Push the switch then power is on with red light on Push the switch again then power is off 2 VOLUME Control the loudness of the Click sound of the keyboard and speaker volume 3 MODE switch This switch selects characters line mode 1 80 CH line o ao CH line 4 RESET switch RESET is triggered by this switch and stops execut...

Page 9: ... i f 1 a a Htl rf f if f t 1 g f f f q V _ F Cassette tape recorder CASSETTE Interface W ex a sion _ I F 1 513 Qlight pen DPW __ Light pen BAP 3700 fiCblour monitor i coLoR colour monitor c14 2170 MonochromeMonitor H ww B Green monitor KIZZDSSP 5 ins zazc Rs z32c Other equipment which has RS 232C interface isprinter PMNTER The six pairs of interface expansion connectors and two connectors are insi...

Page 10: ...NLSMP IC23 IC31 IC44 1C91 inverter IC100 HD74LS05P IC22 lC95 ICIOS open collector inverter xczs Icas xC49 IC92 HD74LS08P IC96 IC136 IC143 2 input NAND gate 1C14s HD74LS1OP 1C21 rC4s 3 input AND gate HD74LS11P Qrclss 3 input AND gm Q H D 7 4 5 1 4 P Cm QStghmitt trigger inverter V HD74LS30P rcso ICIO4 S input AND gate Q HDm S32P 1C29 1C3z IC97 1Cl44 2 input NOP gate IC14 IC1s ICI7 IC1s HD14Ls74AP I...

Page 11: ...C113 IC114 data Seleeterhultiplexe __ _a HD 5283 1C4 4 bit Q decimal adder 1c1 ics rcs Iclo 37 HD74LS367AP xcle Iczo IC41 lcvs bus driver IC79 Icso Icsa IC139 1c14o Vi HD74S04P IC43 inverter E H 3 7 4 5 0 5 IIC132 J open collector inverter 40 SN74S163N IC37 4 bit counter T Hrmosp IC135 open collector inverter Z Hm41s3P 1C52 xcsa IC54 IC55 data Selecter multiplØxe 43 HD74159P IC86 decade demultiple...

Page 12: ...dummy access or VMA cycle Address are valid on the rising edge ofQ All address bus drivers are made high impedance when c i l a b l e B A is High Each pin will drive one Shottky J L bJ 4l LJIJJ FXVQL TTL load or four LS TTL loads and typically 9OpF d nication with the system bi directional Data Bus D o D7 These eiggt pins provi e commu data bus Each pin will drive one Schottky TTL load or four LS ...

Page 13: ... Available Bus Status BA BS The BA output is an indication of an internal control signal which makes the MOS buses of the MPU high impedance This signal does not imply that the bus will be available for more than one cycle when BA goes Low an additional dead cycle will elapse before the MPU acquires the bus The BS output signal when decoded with BA representing the MPU state valid with leading edg...

Page 14: ...be valid with the leading edge of Q Data is latched on the falling edge of E MRDY This input control signal allows stretching of E and Q to extend data access time DMA BREQ _ The DMA BREQ input provides fa method of suspending execution and acquiring the MPU bus for another use Typical uses include DMA and dynamic memory refresh When BA goes Low the DMA device should be taken off the bus HD45821E ...

Page 15: ...ts that can cause the IRQ line to go Low Each flag bit is associated with a particular peripheral interrupt line Also four interrupt enable bits are provided in the PIA which may be used to inhibit a particular interrupt from a peripheral device Servicing an interrupt by the MPU may be accomplished by a software routine that on a prioritized basis seqentially reads and tests the two control regist...

Page 16: ...ndCB1 Peripheral Input lines CAl and CA2 are input only lines that set the interrupt flag of the control registers The active transition for these signals is also programmed by the two control registers Peripheral Control te2 TheD91 iDh91 controllineCAcanbeprogrammedtoactasan control line CA can be programmed to act as an interrupt input or asa D9fiDh9 5l control output As an output this line is c...

Page 17: ... is a TTL compatible open drain no internal_pullup active Low output that is used to interrupt the MPU The IRQ output remains Low as long as the cause of the interrupt is present and the app ropriate enable within the ACIA is set Clock INputs Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data Clock frequencies of l 16 or 64 times the data rate ...

Page 18: ... of carrier when the Receiver Interrupt Enable bit is set U p i narrangement GND Vss RES LPSTB MAG MAI MA2 A4 MAS As MAT MAB A9 MA10 MAH MAI 2 MAI DISPTMG CUDISP 5VI Voc _ E E E HD46505SP CRTC EE v svnc H svmc nm nm RA2 mu cn oz I I l I Ds I Es l IEE mw Ell CLK CRTC 3 CRT Controller ll 4 5 B EH MAJ RAA M El Do E EE M IE gn Ill so D3 2 29 D4 M Il as os IB 27 S 25 D1 E as if z as 23 E I FUNCTION OF ...

Page 19: ...er scanning It is necessary to enable video signal only when DISPTMG is at l l i g h level Refresh Memory Address MA0 MA13 _ MA0 MA are refresh memory address signals which are used to access to refresh memory in order to refresh the CRT screen periodically These outputs enables 16k words max refresh memory access So for instance these are applicableup to 2000 characters screenand 8 pagesystem Ras...

Page 20: ... is Low active and content of the memory is outputted to data line Basic and Monitor System Program is written in three pieces of ROM uPD2364C 331 pPD2363C 332 in MB 6890 The Address is allocated by ROM Address decoder as shown table 5 2 TABLE 5 2 R OM I Address 1PD2se4c aao A oo o s BFFF PDz3e4c 331 1s c ooo s n1 z 1 i v A Q QQ u P D 2 3 6 4 C 3 3 2 L UU 5 bb s FFF o s FFFF The block diagram of t...

Page 21: ...AO D0 D DZGNU M _ A Address Bus m_g Data Bus f5T CSz Chip Select Fig 5 8 uPD232C 328 is 4K Byte Mask ROM Read only Memory and used as character generator in M 6890 1 Memory address of 212 4 096 4KB is selected by 12 address line A0 All 2 The content of the memory is out putted through 8 data lines DO D7 Fig 9 1 1 ...

Page 22: ...vugeavgns Fig 5 10 5 10 consist of 4 pieces of 2 input NAND Gate VCC GND pin wiring in IC is omitted in drawing VCC pins connect to SV line and GND pin to earth line 5 11 consist of 4 pieces of 2 input NOR Gate Quadrupie 2 input positive _ NOR Gates vcc 5Vav ag 4 3 Ja M _ QTQT ii u v PA g 21 25 Gm Fig 5 11 ...

Page 23: ... Output sw vc SA 51 54 5 A Y 5 lF l II IH ll ll F li li u II II I IA nv Fig 5 13 5 13 consist from 6 pieces inverters Each Inverter is open collector and the resistor to each output pin is required in MB 6890 circuit drawing different mark of Inverter is used for open collector WDC I _ Output Regulator Inverter v Open collector Inverter Open collector Inverter Collector is directly outputted Fig 5...

Page 24: ...15 consist of 4 pieces AND gate Triple 3 input NAND Gates ve IC IY _Sc 38 IA 5v 14 I 12 1 ro 9 3 W I l 1 S V C I 7 ll IB ZA ZS 2C ZY GND Fig S 16 5 16 consists gf 3 pieces NAND gate I O truth table is as shown fig S 17 Input Output Q Y c In ut utput V A p B l C Y L L L H LIL H H L H L H L H H H HLIL H HTL H H HlH L H HIHIH L Fin 5 11 U ...

Page 25: ...elow in Fiq 5 19 Input Output A ____ B Y C _ lnput Output I A I a c Y L I L I L L L L H L I L H L L L I H H L H H l L H H H H I I H L I H L I I Hex Schnutt TjiggerInverters ISI Vcc SA SY SA 5v 4 5 gy I Ii I I I I I I I I l If ZA ZY BA Sv Quo Fig 5 20 5 20 consists of 5 pieces of inverters The diffgpengg from regular inverter is the Input voltage when output goes H L and L H Inverter for the input ...

Page 26: ... J f i L V C33 T8E1 3527 EYSEEM In MB689O circuit diagram two inverters are shown opposite In figure 5 22 8 input NAND gate IC Ouput goes L when all the Input A G are H Output goes H when one of the input is L Figure 5 23 CUf SiS CS of 4pcs of 2 input or gates Figure 5 24 CDl 1Si5t5 of 2 pcs D Flip Flop IC s The Data is the input D is read at rising edge then be transferred to output when pre set ...

Page 27: ...ainsprevious condition as edge of clock CK does not rise D 0 5 25 HDHESSSVEQ Quadruple 2 input Exclusive OR Gates SV Vcc 48 4A 4Y 38 3A 3Y 4f Lai Ve v Lo is s 2 3 4iA5 s 1 IA I8 IY 2A 2B ZY GND S 25 Output Input Output D D Y a 5 27 H L _ Input L L L L H H H L H H L Q does not change even if D changes when CK is H period 5 26 consiStS OF 4 pieces of 2 input exclusive OR gate I O table is as per fig...

Page 28: ...ip between reset input l 1 L I L L H Ro 1 and Ro 2 in case of 16 digit counter is made V connecting output QA and input B is written at table 2 I L L _L H L 5 4 and table 5 5 3 L I L H H 4 1 L I H L L Output changes its status at falling edge of the 5 L H L H s L H H L L 7 L H I H H H 8 H L H L L 9 I H L L H 10 H L H L H I H L H H I N 12 H H L L 13 H H L H 14 H H H L H H H _ H W di it out ut digit...

Page 29: ...e decoder Ougmt One of the 8 output line of 3 select input and sv Y _ 3 select input and 3 enable input The I O v Y ___ c _ _ t e i relatlon lS as per table 5 6 1n next page z GB Q YI Yz Yx Ya Ys E m I3 Z I O 9 vo vu YI YI Y Y A YI 5 Yr 3 C G A 1 2 B B 6 8 A B C Gu Gil G Y GND sem input Enabw input output 3 30 Hnz msiaseir Dual 2 Line to 4 Line 5 31 COF sists of two independent 2 line 4 line Decod...

Page 30: ... 1 L H L L H H H H L H H H H Hl L HITTHIITIH H H L I H I H H L H H L H H IH H H H L H H L H H H H HIH H H H H L lG Gu Gm X H Acceptable both H and L HDNESISIP I of 8Data Selector Multiplexer with Strobe sv I Dafa inpult DutoASelect1 VCCQSSTABC IS B I4 B I2 I so Wg D4 Ds Dc Dr A 3 D C D2 Du 99 Y W 5 ___ 1 2 3 4 5 s 7 3 3 2 I o Y w sr ooeGND ww input output table 5 ll The I O relationship is per tab...

Page 31: ... xx H I L L L L I x x Ix L I L L L H I x x x L H I ILIH x I L I x I x L _ I I I L _ I _ I __ I I I I I I I X I I I I H WL I x x L x L I L H L p x x H Dx I L H I H I H x x x I L A L I L I HI H x x xIYH I L H I Acceptable both H and L g OR In ut I output G I A a I Y I H I x x I L I I I I Value of Co L I L H I Value of Cf I I H L Value of C2 L I n I H I Value of 3 OR by other expression Co Cx Po I Sw...

Page 32: ... Strobe Select I A B I Y H x I x x I H L I L I L I x I H L I L I H I X I L JL I H I x I L I H I L I H I x I H I L I X H Acceptable both H and L 5 34 is data selector multiplexer which select one data from two having 4 pairs i one package Strobe and select is common for 4 outputs When strobe input is H all the output becomes LI if strobe input is L one input data is selected then transmit to 4 outp...

Page 33: ...Qutput Q O Q 1 5 is open collector Q QJQtQJQnQ QJ L L I I IUPUt Output G G D c B A Q Q Q IQ1i Q Q Q Q1Q ILL L LL LLLL LHI L L L L L H L L LLLLHH L L L L H L L L L L L H L H L L L L H H L L L L L H H H L L L H L L L V I I I I I I I I I L ruvvu _IL I I I I II Jll lIlIIII L H Therefore G1 G2 L is required to I operate decoder Lux L _ L to LLHLH H L LLYHHLL I I I LLHHLH Lo LLHHHLI I LLHHHH IL Lnxxxx E...

Page 34: ...er is 1 preset programmable Preset can be done with synchronization with clock When applying L to the orad input data is outputted which shoul be matched with input data at next clock pulse regardless enable input level Clock Enable _ _ I p Enom I Lock function is synchronous with the C i C 3 C i I n _ _____ and if the clock input J S L each flip 1 I QA _____ _ V Q f LL as O _ ____ _ _ output beco...

Page 35: ... and the data is shifted at the 2 1 l rising dege of the clock pulse V_B m m _W m_ W0 The time chart is in 5 LO and 1 H P u t _ _ Output the function table in 5 13 5 39 Clear L_ A L _ Seri a _ I V1 input _B Clock I 4 r 1 QB 1 _ _ F11 Qc 1 13 _ r 1 Oo 5 output If I f os ___J Q 1 11 Oc II r t _ swtiming HDMLSm4P Table5 13 HD74L SI64P 7 71 bfi ff Clear i Clock A B QA Q B _ ___ Q _ L X X X L L L H T H...

Page 36: ...rst clock This clock is synchronizing with parrallel inputs Then input is shifted by 1 load period when not shift and if L CR is independently rising edge of clock clock A H to QH in order during clock inhibit CI I I clock will level shift can be done Clear valid when CRFH shift is done at cx n11a 11 I 1 Q Clear _LJ f f Seria 3 Q 3 Q sr1 f1 tm f 1 E A 1 3 Q I 1 L 1 1 1 C 1 1 1 1 5 1 1 1 Pm11 1Out ...

Page 37: ...ist X Acceptable both H and L Rising edge _ Qo Qo Previous status of Q 5 Ala consists of a lines Flip Flop Difference betweer HD74LS1Z Pand this chip is the existence of reverse output Q pin The I O relation and time chart is the same as HD74LSl74P 5 45 Consistsof Bi directional bus buffer 8 input output By enable input Ei Low and setting direction control DIR signal transfer direction A B is swit...

Page 38: ...output control is H all the outputs go High Impedance and when L output the status data B if select is H If select is L output the status of data A 4 bit adder Each bit sum is obtained by the B m B B B m m E Z output The signal from 4 bit output or more higher bit can be obtained at CL output Bs AJ 2 44 B4 I I C B1 It 2 M 3 5 _in _3_ 4_ 5_ 767 S E2 B2 A2 2 Al Br CO GND S 47 547 Sma Out ut C Lo C H...

Page 39: ... U T B J ell n B E u B U n 5 49 CO siggs Of 2 pairs of Line Receivers Aa Bu NC vu Ge 5 GMI 5 49 Power is 15V two supply when op input A B is 548 more than 25mV amplitude TTL compatible logic level _ Strobe Gut signals are outputted put V ND A B G Y S Y vmzzsmv 1 x I x H X L H 2smvzsmv III zsmv III l l U f ll 1 ll A x L H vm zsmv H H H L X Accept both H and L _HDZ5188l Quadruple Line Driver 5 Iva 4...

Page 40: ...ed 4 2 3 4 5 W lr IA cPntrol2AcontrQ G g 2 5 vcc W 2K 5 V I V Y 4 Jntrol input input_ A Slin GND S2 Circuit C I iming resistence connection 1 Tir ng capacitor connection 5w NC NC NC NC ve E1 El El El B El Pha e 21 EXE Det Ctor El n u u n wr lHDUtVCOOUE V60 control voltage hsvv T pu _ 1 Standard Output Reference Phase Comparator VCO Input 5 53 5 53 Consists of 3 Blocks 1 Phase Detector 2 VCO Voltag...

Page 41: ...necti I Øweeai _ _ _ _ e I BREAK 1 RAM I 0 0 BLOCK M Keyboar ll I _I T Cassatt Acm olour I Ho4ea5oP bill I egiste ___ _ ideo D A I ØggiØfor C3558 t s zszc OC Pecorve F T VF A ll I s c B I gggØgggiq Ølsoiilgfection U E eri o our Corr o i e e e C l n S I araiØel iØeo siggai Princ r I OW C an e eneliØto ge erat r PIA _ gngggg o driv Ho4ee2 P i gg _ _F __ L _ _ _ _ _ _ __ _ ak V Sneaker Q giharacter g...

Page 42: ... one of page 40 44 missing ...

Page 43: ...ck by this signal CRTC generates the Address MA RA signals Horizontal and vertical synchronise signals and cursor display signals and bridge the data between MPU 3 RAM Block RAM block consist of 32KB l6KBxl6 Programme Store RAM and l6KBx5 Colour Store RAM Colour RAM and Program RAM occupy the same address therefore the signal receipt and sending between colour RAM and MPU is done through colour re...

Page 44: ...U data bus 7 RS232C Interface Circuit In RS232C Interface Circuit l6 l28 MHZ clock divider generates the receive send baud rate and Sends this Signal to ACIA as recieve send clock In case or sending according to the set baud rate the data signals from MPU is sent by converting to serial signals and v i S V f S in case of the receiving recieved serial signals are converted by ACIA and outputted to ...

Page 45: ...lel16 sl 1 _ BMISS Us sr HR KN Q Table 6 4 Iggy Fm KB l D D D D D iD D Do 0 1 mga I The DIPSW register to set initial condition of only When Power is ON 6 3 Address 0200593 Block 6 3 1 Internal Resistor Structure In basic Master L 3 above hardware registers are incorporated _tDachieve the various functions The functions of the main registers GTE GS explained already the Basic language read Mode Be...

Page 46: ...F 1 1 Fs __ E E T FWO IC41 rcgz 74LS367AP 1 GZ I Q _ IC2 W T 7 4 _ s 3 e A P I IC95 EXTAL W I _I F5 4 o32MH 5 2 MPU Circuit 1 Data Bus Do D7 Bi Directional which are directly connected to ROM RAM PIA ACIA and CRTC conducting the receipt and sending of the data to MPU Through IC6 these data bus signals also conducts the transaction of the data between system expansion connector I F l I F 6 memory e...

Page 47: ...rcuit shown at figure 6 3 Input of ICII has upper 3 bit AB15 AB14 AB13 of the address bus are connected At the Output YO Y3 of ICII L level signal is outputted as the block of 2 000 address from address 8 000 When ROM mask signal ROMKIL is H level dsssds signals are outputted as per the allocated address in Table 6 5 below to 20 pin of IC2 ICQ These ROM IL signals comes from system expansion conne...

Page 48: ...ess signal which is outputted to the RAM extension connector in the main unit is also decorded by ICl37 The upper 5 bit AB15 A1311 of the address bus is inputted in ICl37 and output of ICl37 ILYO 1Y2 ZYO 2Y are outputted to the RAM expansion con nectors mhich correspond with the address shown table 6 7 Therefore in case of expansion the RAM no further address decording circuit is required Table 6 ...

Page 49: ...e v e 1 A B A Yu A84 5 Y2 ABQ A B C Y _ ABS 5 Y l 4 9 cans G Ye ABIS Br 5 m Y Fig 5 4 System I O Address Decoder Main Parts Table 6 6 ICIZQ Decode Address I YFDEQCOCIE AddreSS S 1 Y f _ res Decode lgna S Y FFC SFFC7 Table 6 7 HAM expanslon connector 1 FFC8 5 FFCF Yf FFDO SFFD7 ui ut _ _ _ __ yi 5 FF D8__ 5 FFDF Signal Qxpgnsion Lf ress Y SFFEO 5 x F a v A89 5Ef RAM 3 ssooo s QFFP Y S FF s s F F E ...

Page 50: ...riod fw s_oe4MH1 4Och Mode not X40c d Bdoism d Frequency orizontal isp ay perio fCw 2 016MHz 8Och Mode Character Frequency Dots f C 1 5MH1 4Och Mode Character tv 1 1 q u i 1 C Y 0 fr 1 008MHz MPU Operation Clock Frequency f m x r 1 4 0 3 2 M H 1 M P U Operation Clock Frequency o f 15_75KH2 Horizontal _ Synohronise 4 U v 60Hz a g a r e q u e n m 3 a i 1 Ø e L 1 1 1 C f 2 5 c43 IC37 c i cas ncaa H D...

Page 51: ...used to make the 32 256 MHZ oscillation easier 32 256 MHZ clock is divided by divider circuit IC37 to 16 128 MHZ IC37 14 Pin 8 046 MHZ IC37 13 Pin 4 032 MHZ IC37 12 Pin and 2 016 MHZ IC37 ll pin 16 128 M H Z i s used for system signal generator display DOTCK signal 80 characters and RS 232C clock 8 064 mHZ is used for the display DOTCK signal tt d from 40 characters 4 032 MHZ is used for EXTAL sig...

Page 52: ...1c4s4 74LSo2P MPU D sP sw Fig 5 8 System Signal Generator Circuit 62 5ns BODOTCK I I 15128 mPZ_ n C38 3 Pl gala 4 l25r s _ sa n1 I 1I p 250n 1 I I I I I I C1 3 pin di e I Ius s E P6 Mpuperlo an 61 _ P111 I _ Us I T1 I AOCHRCQ I cae pln I I II I I BDCHRCI l I I lC38pln pln I _ A 40 I 4 I 86005 I I I LoA o 4o M0331 S i I I 038 Li I y 30 I I I L 6 A o s o Modal 7 Il I S I g I c38 Z P 1 Us I l20ns I i...

Page 53: ...bit shift register IC 117 HD74LSl66P The signal for 40 characters is composed of output QD and QH of IC42 and one for 80 characters is from QF and QG 3 GRENBLE 40ch IC42 13 Pin 8Och IC34 10 Pin The signal to control the input signal to the Enable pin output of graphic generator and also to prevent the overlap of the output of the graphic signal output and character generator output The s gnal for ...

Page 54: ...CRTC E TTL signal for the system clock is inputted to E terminal and CHRCK signal for the clock signal of display address signal to the CLK terminal Data bus is connected with MPU data bus Fig 5 8 CRTC Internal Register Structure Address Name of the 6 RS RSglSt r R e l i S t egiSter READ WRITE 4 3 2 1 o g 1 x xxxxx on Valid o o xxxxx AR egfgigglt X 9 o 1 o o o o o R0 Egrfifcghgiacte X O_ o 1 o o o...

Page 55: ... 115H fl ie 53 5 S vsmc _ VI C36m I 16 5315 ri spme 9 I wus on _ ugggnpln H s c Q1 63 5115 l 5m5 v L__ lS 6ms cunD 5P _ I I I I a u f c h m o d e I n f i i 1 5 6 f 4 auf ch mode I n f i i 1 5 6 f 4 ac ch mode 0 5 S 15 GMS 6 ll HSYNC VSYNC DISPTMG CURDISP Output wave form time chart Mm mm 4o 1 de IIsa de I i 4 soons NG MAL I lu w l 1 l I 2uS I MA MA i us 14 MA MAJ II Sus I MA MAA il F i g 5 2 Refre...

Page 56: ...fiPlX L V L I 1 RAA1 flcxas QPU f 5 5 lcharacter vertical cycle MA P151 P151 Mn AO circuit Fig 5 5 The roster address output wave form after switching Fig 4 ICSI Output signal mo ay Øiara c h 80 ch xcsx s Eilgut L H vfuru DA A I L u L Iput l nx H cm 2Y EE RAA RAA xcm aYg RAA1 RAA rcsl 4 Y8E Ø L RAM eo 40 ICS HRSO SW N40 74L5157p 74LS2B3P nam A 5 S MAD M RA U cnrc Mau A2 RAA3 JA _ Mm A3 I M MAL Ad ...

Page 57: ...s of each mode in CRTC is shown at IC49 and ICSO is the circuit to s on at 80 character mode t tching circuit To switching of the interlace mode vertical direction display mode and the non interlace mode is done by changing the write value in internal register of CRTC The raster address RA0 RA3 from CRTC has different raster address value in each mode which is described at CRTC block chapter In th...

Page 58: ...he is inputted to G input of of C5l Therefore upper the CRTC is still connected to the display address as shown in fig 6 17 and make one character with 8 byte address This address conversion and switch circuit Fig 6 l6 SW H level output lY 4Y level is inputted to E input of IC5l tha raster address RAA1 RAA3 as shown at fig 6 9 are outputted to the each output lY 4 of IC5l by character display mode...

Page 59: ...lay address bus between RAM and CRTC is connected as display period The bus change is done by MPU display address switch signal MPU DISP SW signal The RAMS HM47l6AP 1 in use in this system is addressing input 7 bit Dynamic RAM To use this chip as equivalent as address input l4bit l6KB Ram input of l4bit inputs should be separated to 7bit low address and 7bits column address Each address should be ...

Page 60: ...U dis Kddress RØafeØag a a g gE Øa witChingLow column addre switching signal signa G l9 RAM 2ig5 w Output address of CAS signals R A M lsignall MPU period gØegjggy FIRST RAM IC56 IC63 CAS1 so 3FFF 5400 sgppp SECONDWRAM IC69 IC76 I CAS2 4000 7FFF 4000 43FF cqnoua RAM cAscR 400 s4ax 1 400 5435 R A M _ A d d r S5 __ StOI Sp AM l L CQ _Qur Y g 23476 IC64 68 M GAP HM4716AP 1 1 P _ Q V L _ kgrf 1 1 Em L...

Page 61: ...ree state output latch capable read write to MPU and used for read write from MPU to colour RAM through direction each one piece of three state buffer IC78 79 HD74LS367AP The RAM common address are allocated for store RAM and colour RAM but colour becomes valid only when the registers access the display area in store RAM Following is the general explanation of the operation 1 Display Period Displa...

Page 62: ...n Therefore the complicatedpattern of 128 varieties are recorded in area 1 6 6 2 Graphic generator circuit Graphic is divided into high resolution mode and regular mode This mode selection is done by the HRSO SW signal which is outputted MODE SEL register IC39 2 pin Fig 6 24 shows graphic generator circuit In fig 6 24 HRSO SW signal is connected to ICll3 ICll4 If HRSO SW H high resolution mode is ...

Page 63: ...Co1ourRAM G Data B_t B cuaetc _ Ionochrome E V video 5 ideo S Slgnalt si nal RE ge era ll Q me QC generat r ra hi engra r CU lrcul D _B muv Pro ra to e MM 9 gaia glt G Brl h n s A I 0 Øge at r P Do lC107 g N haracte enerato C W S I _Hsmc sXnchioou s gna v svvvc ge er t h PEDSTL H svmc r mme V SYNC Cl34f Fig Ql Video signal 61 Q I 1 I t O I onochr me 033051 e V1 o s1qnal Raw Colou slgnai r video ...

Page 64: ...pt Z J H 5v _ _ Doo C a m us as M DDI oC no DD _gg si c1 12 DD4 Y I zco CUZ 9 74 __3153p D05 _ acl av 232 ll lll U SØi II A 5 GND Ill I4 2 B R R23 lll lll I lll sv axcszs 5 4 SV GR 535 4 Øs zasa g 4zA5A4A Vcc e Qazasaaalpzasnu Vcc vs ICI 3 U ICI I4 HRSO 74L 257P 8 I 74LS257P B Sw Swzf suv G S wav suv Gm ii cm _ input Fig S 24 Graphic generator 62 ...

Page 65: ... signal to 9 pin of ICll8 are done After reverse buffering these signals in ICl32 colour display colour raw signals R G B are outputted to colour display connector 5 R G B signals are composed with synchronous signal which are made from ICl32 and ICl35 at A converter then after impedance conversion Q5 these signals are outputted to mono chrome video terminal 6 On the hand synchronous signal is cou...

Page 66: ...5 5 L C E 5 41096 lgfgq o 10 35 _ m _ vcc 12 SYNL _ gx on brl ht ess cI34m 3 3 i s on _ 1018536 ICG Ar 5D HSN 1 m 2 2 sw 14Ls9aP 2 f 3 f 2 9 8 5 3 916 52 _ _ W S ISS Jn 3 nz gun _ PUA I ICB sms _ FICH7 I5 T3 O azlcmqo _ ___ _v I4 3 vw 5V Blcgq m o o Pau su e no 5 5 GND Pun 2 an M a o IC117 oo o o H me 1C 3 _ IC94 ICI oo lc as SN74L 66N H ZCKZPSZO 74LS02p 74 _504p 7405 P U 1099 rms VSVNC PUD I2 I3 ...

Page 67: ... by software 6 When the keyboard read signal goes H after reading keycode in MPU three state buffer becomes high impedance IRQ interrupt is released then X counter drive startsafter opening HP signal gate 6 8 INTERFACES 6 8 l Cassette SAVE load circuit RS 232C interface circuit 1 Cassette interface RS 232C switching circuit In cassette SAVE load circuit and RS 232C interface circuit ACIA IC84 is c...

Page 68: ... I s V matched signal _ V E at D 4 rn 1 H 3 I f Y Y 7 IC88 74LS367AP C98 74LS125AP _ ___ L U A lC86 m PECUUER 741s9P mm WU ICIOI l c1o2 _ I ig m eyco 4Ls93P a s _ __ CI carry out Y t e r ICIO2 HDGBOQP HP IC97 14 ssar 9L Sianging gounter sto I A C OC _ r1v wltc k b 511 H1111ev a d 511 H1111 ev a d drlve slgna _ IC99 aqinterrupt 74LS74P IC96 74LS08P RQMAsK Fig S Z8 Keyboard ...

Page 69: ...B 1c92 _ IC92 c91 ICI 25 CSS piri mai pin 74LS08P 14 _so4P 74 sooP 4 5 Fig 6 29 Cassette RS232C Switching CiI CUit 6 I4 RS C Sw Signal and each IC output ICl11fi pin r H H IL RS C SV ignaI assettgas zszc as 2320 Cassette IC1IlfiPj_n xe 12sMc1 1 oosMc1 _ 9_2 YCK ICl1l Pin ØsifconneØggdcggei 9 5K c K C111 Pin TT D g a te output I I ICl23f1 D Pin i 53_5KCK 9 6KCK I IC124 Pin 76 sx 4 sxg ICl24 Pin 3s ...

Page 70: ...r I f utput_j LJ LJ LJ ncxzs output Fig 6 32 Cassette LOAD circuit Fig 6 31 Cassette SAVE I O timing 5v I W R409 CZI9 cassette cmz 5v l load sig 9 lo 8 _LCZIB lC2l5lC2 641_C2l7 ICZIB _L _ czu 55 E Zora 2 v r I I _I MI f ll ICIZ7 was Rav nee E 9 9 tg H3111 R I 6 Q33 1 T Qi oe nas L C225 _ 3 I TPB TPM 27 _ canal ICI 28 _M555 N 5V nsv 75108AP _ H levelJ4 L level YLMWX4 Lnmxz wav wav s 417us 3335 4 zc...

Page 71: ...rate is required between connected equipment and signal lines The meaning of the signals which select sending receiving condition is as follows TxD signal sending data signal to outside equipment Output TxD means low logic RTS signal The signal to request data to send to outside Output RTS signal means low logic DCD signal The signal which shows that sending from outside exist If earthed Input The...

Page 72: ... duplex mode In the case of receiving sending serial data Start bit at the head of each character and the stop bit at the tail of the character is inserted to distingula each bit of the data and character block Fig 6 36 shows the principle of this method ACIA sending operation After conversion of the parallel data inputted from data bus DO D7 to serial data start bit stop bit and parity bit is add...

Page 73: ...Data Reglster 1 _ Y _ datal wr re atamf The micfcile of last stop bit cS RS R w E remarkmne flag ACIA Igtgigal flag If this flag is set data transmission is T1 Dm R S S C Ø 1 e r a a r g g data converted from parallel to 216 7 grincipal 0 ACIA l2345STBl234567B9 O lI2 3 4 5 6l2 7B9 0 2I3 4I5l6l2345 gi f 1 H H H 1 l I 1 f I U l H l H 1 1 H I f H F I n l 1 f 1 l 1 f l T H f 1 f f l l U l l F l l JU u...

Page 74: ...vel Then transistor Q4 goes ON and the cassette recorder becomes in operable state by closed relay If REMOTE and D7 are L level the cassette recorder is non operable 5v 5v ag 2SC1213d 4 5 D 2 D we 5 R77 Y Q ICIZSIQ Q RU ReMoTE m K U S I 1c a are Q 4 an L J s JA C 26 2 3 14 s14AP Sion 2 Fig 54 Cassette remote control circuit 6 8 2 Printer Interface Circuit In printer interface circuit PIA Periphera...

Page 75: ...nterface circuit This circuit is the interface circuit to read the position of the Light Pen on the CRT The content of each terminal of I I 1 JC is shown in Table 6 16 When the light pen is pressed LP SW becomes L leve and LP OUT which indicates the timing is outputted After LP SW and LP OUT are inputted to pin 12 and 13 of IC25 inputted as light pen output data to pin 3 of IC17 After that LP STB ...

Page 76: ...input terminal is incorporated before the sound amplifier circuit Fig 6 I6 Light Pen Interface JC I O pins JCpin nol signal content 1 I fJTI _ pen ir2 I WW lf a S sse H 3 I _ 5 V Power E U VCMP i i 3i 3l g h 51 Sin e e er d when Y e EØgØ pen kiiØ pin S m l vertical sync LPOUT in nczsri P p_ f _ 3u Q _ H H H horizontal sync 4 63 5p 6 6 m LP sfe _ lC17 5 P n 6 6m me _ C1B pil i _ _ Fig 5 43 Light pe...

Page 77: ...nal RAM3 at the address 800 9FFF Also ROM KILO signal inside the unit becomes H level and ROM IC2 becomes non operable and instead of that data buffer IC6 becomes operable then RAM expansion PCB data bus and the one in MPU can be connected On the other hand ROM KIL signal outputted from memory expansion terminal is outputted as EXROM KIL signals on general expansion terminal this signal becomes H ...

Page 78: ... 2 2 _ _RAM _ A RAM RAM mx J V 1_ _E_ n erna 1rd RAM lC2 x anslon _ f _______ K b tØ A Raid __ usbyte ma 3KbytØ _____ ______ A FBAQC BASC W4 R0Marea R0Marea t h mbyte W ____ l 2 b Y t _________ __ Ø V f f i V f f i 1 structoge of each element 3rd R m occ 8 the internal The ogher aiea expanslon area exceg monØgr li o cuple y Fig 45 Memory map of system expansion 76 ...

Page 79: ...lnal pg C X RWE C000 SEFFP select Ølg 59FFF addre AR RAM _ R xsxbytg EE nc cs A9 _ C 5 select serrs pAMexpansi n PCB xca Waco sv sele t 1 F DFFF A _ C S general expanslon termlnal ucs F R M 5 cs y sefaoo 1 0 TS F e l i i l F F F EXROMKIL gddress 1rcu1 ROM K IL ROM systemexpansiPCB system expansi PCB noM lnterface PCB nth ROM1n 11 t sic PCB _ sv L sys em expan liiiiini Fig 6 47 System expansion int...

Page 80: ... leak to AC power line such as by power unit y Regulator circuit bridge regulatesthe AClOOV by DI then charge Cl 5V regulator uses Single forward method which uses switching transformer TI and switching Transistor Ql Ql is activated by pulse transformer T3 _2nd pulse of switching transformer TI is regulated by D100 then DC output can be obtained to ClOOA and ClOOB through choke coil Tl0O h i n v e...

Page 81: ... have the synchronise operation as IClOO master and as IC 200 slave Therefore it operates under the triangle wave generating circuit which was decided by IC100 p For that reason internal oscillator in IC200 has short circuit of 6 and 14 pin of IC20O to prevent operation IC200 outputsthe pulse output to pin 8 and 11 which are controlled by inbuilt 2 pieces ofPWM comparator output similar to SV supp...

Page 82: ... the voltage to pin 15 and 16 of IClQQ In case of l2V supply the detecting voltage generated in RZO7 is controlled through inputting to 15 and 16 pin of IC200 l2V 5V supply over current protection circuit in 3 terminal regulator IC4OO and IC3OO control the output current in rated range 3 Over voltage protection circuit If one of the 12 5 12 and 5V supply has over voltage THl3O becomesoonductive an...

Page 83: ..._ _ _ _ _ _ _ 1 Fig 7 Memory map in standard Eon qu Conflguratlon display RAM area user RAM area I d 1 user area display mode 1 aØgp ay head add ess W ch normal xx byte 0 3 3 normal zx byte gps w _ high resoll BK byte ana B0 Q f l6K 755 Fig 7 7 31 16 decimal i l f PM AOA 1 _____________ CRTC I _ _____ _ i KB NMI I l DIP SW _1_ l_ UMER I l1l I L PEN FLG ___ open MODE SEL __ TRACE REMOTE MUSIC SEL T...

Page 84: ...etween no 5 and no 2 terminal of the cassette I O jack JA under the cassette cable is connected to the main frame of the Basic Master Level 3 the signal can be inputted to the point of ack ll t the mini jack Oscl a or as Fig 8 2 wg te earth line Fig e 2 JA _JC 1 l TFT6 TPI3 TPH 1 jggirj E if _ _ Q0 L V1 ug _ wk e e f _ _ _ my 7 fa 13iI1 A _ _ E a u e S 3 _ r m _ _ 2 J a e A ILP a J 1S _ i f __ Eg ...

Page 85: ...t Fig 8 4 If the grade number in the unit and the service M U grade is the same just replace the MPU If not the jumper wires and C187 maybe required according to table grgde no U U _ rrnrr printed place I r f Z zf a Fig 8 4 _grade JT2 CH7 l necessity of ju per wire j M Fonneqt DECESSLFY JP8 JP9 JPN I CD fi X O i x x 2 CD O O x x 3 D fi X O x x 4 D fi O O x x 5 C D fi O x 0 Q 5 C X O x x 7 D fi O O...

Page 86: ...omponents is done this power unit require adjustment l Disconnect the A connector from power unit and connect the dummy resisters load to the A connector er unit 2 Power ON and adjust the Pow I I two power voltages by szzxxn Connector changing the value of VRlOO H and VR2OO voltage adjustment A volumes as shown at Table 8 2 A The measuement of the power voltage is carried out at the f V K f each t...

Page 87: ...emoved as an E f 5Q7 I arrow direction The Fig 9 3 shows 3 Ø 1_ f HV the photo after removing the cover fe Q v f _a upper cover pair Fig 9 3 I F panel A p lk 3 Remove the panel support plate wp _ Q J fito upper direction in Fig 9 3 L u igg _ 33 _ Then panel A can be removed p fgx9F Tinnext p fgx 9F T in next 1 vi 5 _1 ie _ 1_ A VJ _A _ 5___ id _ 3 _ F f pane1 hold plate Fig 9 4 i F551 3 p _ _ 3 Q ...

Page 88: ...in Fig 9 5 BM A P C B can be removed as Fig 9 6 BM A P4C B f gl 4 1 vvfi H f Q LQ _ 5i 1 fflfi ii A 3 _ V Jn Y 4 Q U 5 7 _ 1 1 f r x r We i w ii 0 ir _ F _ ff L T v A we Q f ff _ B v x 16 1 6 By pulling P C B can case 7 Remove the Fig 9 6 the BM A P C B to arrow side be taken out from the shield keyboard screws 8 in Fig 9 8 then Fig 9 9 is obtained Eig 9 9 Fig 9 8 push switch u Der cover air _ P R...

Page 89: ...setting the setting changes are required it should be done after turning off the power ITIL J _ ll _ L 1 _ _ JC JL 1_ J J__ l_ _ _ Ari f v 1118 5 l C L l 1 g GOES IUC C I 1 d I l Q LI LC L5 U U I l Ullrlilq POWEI UN Q 5 i d Janrxectors J Jc Ja im I VI V1 I VI oPe 1 a sa T 5 N T _ L e Uidip switch 2 cm 5 51 41 9 1 m3 cs E csa nz chip Switch n CSi which ml decides the setting ofMODE ms baud rate set...

Page 90: ...as WIDHSO set 40 ch line mode same as WIDTH4O l set normal mode same as SCREENO set high resolution mode same asSCREENl Ozhigh re solution display programmable function key content Equiv CONSOLE o 24 1 don t display programmable function content Equiv CONSOLE O 24 0 O no display i set half duplex mode H mode by terminal mode set full duplex mode F mode by O full duplex set 7 bit ch mode by set 8 b...

Page 91: ... 5 O O O MODE switch correspond with dip switch no l MODE switch select BASIC mode TERM mode Fig 10 4 Notice The dip switch which correspondgwith MODE switch must be open l mode If dip switch is Close 0 MODE switch does not function Example Set the chip switch asC in Fig 10 4 To select BASIC mode and TERM mode by MODE switch dip switch no l must be OPEN l side 3 Chip switch CS3 The chip switch CS3...

Page 92: ...ip is in 4 CTS sig becomes earthed if the tip is in 3 Fig 10 6 In the case that outside equipment is connected through RS 232C communication interface the matching of the baud rate and signal logic to outside equipment is necessary The meaning of the signals which select sending receiving condition is as follows TxD signal output low level RTS signal To request The signal If earthed DCD signal CTS...

Page 93: ...to 3 timing signal generator vas 3 EØion YES sig 433 go to 4 RAM NO 1 YES e2 l 2 e 2 NO data bus gulse i EgQØsgai NO address decoder oircu t w en 1 on YES IGJQ N0 IG I1 1 Et out YES fl E gi slggmil S e YES cu Q _ lse gg NO ar 3_1 _ mn za Q 2 E5 at sae ES 4 E I _ y _ ls 53N _ 1_ cn YES ii CW cu C22 NO 3 ll l l l YES ICH ICI7 NO IS ucse IC X X Defective 91 ...

Page 94: ...2 9 3 1 YES ln Gi le N0 lc X lC27 X No lc X C12 X ncnaa X 91 X 4335 X IC X YES NO S e Q YES n 5 Q 1 t Eine NO ncn X X 2252X 35 1 _ YES cn X egine c29 X N ucsz x ncaa X 97 YES BØ aE 8 lme N0 C97 X c29 X ncs x cn X ICH X 3 X c20 X ncs ca cs X ncso X cm Cu 5 92 ...

Page 95: ... IC 9 YES C46 V IC28 f IC4 o re gn a of 5 33 YES correct si ulse at i i3 D i n vas C4 Y lse t a l pins YES IC38 IC36 C5 IC40 tput IC _ corr YES _ C28 pln c r slgna YES IC37 IC4 IC43 YES NO I X NO ll X X No w _ O sw X I X gi OU ut YES IC4 ICO ICM X xcu X 4 TNQ X Defective 93 ...

Page 96: ...6 lC75 X COLOR I Z P R I N T H I T A C H I sg lnØ t d GOTO 1 2 1 _ YES Puls cw X p e rs a NO cm X C E 53 lem X YES ucsz X S __ css X _ted ucu X No Big 9 css X 4a X YES ncm X _ ICH3 X ta 2 o lt g c 44 X YES X ncaa X Is the t No _ fi __ __Y S i C 2 f P 8 p1n YES ucuz t cus _ S Q __ ucm No pgln cN5 acaz X YES ucas X IC49 X s the u s 1 v dV0 a C e2 4T YES cn X cs4 X css css vcsr css Defective 94 ...

Page 97: ...15pin No C11 pin5 7 1O pulse H inputted t6 YES l29 9 ci 5 X YES cms X N0 cm X NO P1 1lS uczs X utputted fro 116 pin ICIIG X YES vcwl x ncns x ulse nputted mic YES 18 15 _ 1 No utted to 1 g 7 9pin YES per S C 1 3 _ vas cm n colour di a o ucuoo X YES C 32 cm X cuss ICI34 X JB X Defective 95 ...

Page 98: ...pear at Ic99 N0 ln YES waveform should be observed when the key 15 pressed ucn X CH X cn X O 3 NO I 5121 1 a stilke i n 4 NO 102 3 ln _ L ll ll YES w2 chlp connec r keyboard x _ T2 contact x G lCl0I lCl02 X I I No X X N0 8 NO _ ls _ N0 pear at lc 9 X ucn X N0 _ n I X 2 X X I 9 X I 9 X X ICS C97 IC 9 IU YES ulse ear at IC9 YES C88 C8 C 4 lC 00 X Defective 96 ...

Page 99: ...GRAPHIC MODE DEFECT H 7 Q Q 0 iqh ISS YES ode work 2 NO Cuz Cl29 NO IC39 sl ear at IC N0 4 lO l3pin YES C40 ICSI ICH X ICII4 X X Defective 97 ...

Page 100: ...X ucv X uls cm x nputted eve N0 O sec IC1 YES ICN x ulse lnputted ev N0 O sec t IC22 2 YES cu X cas X ICI X waveform should be observed after 11qp outputting sound by program pe _ IC9 No ex 1 BEEPZGOTO1 O I i 5 pin YES ulse lnputted to _ _ulS_ 93 3pid Gal 5 CO OI YES 1 ll I f Q1 QI x YES IC93 x nu X ICU x Q2 X C20 X Q3 X X Defective 98 ...

Page 101: ...2 I record X P YØs O pin norma relay ine wa circuit L tt 09 B YES raigiigaxe correctly djus ICll No 9pin norma R109 ine e misadjus n CH7 X YES N0 C1If l 4 9 pln cg ut rma Cl2 YES nput outpu N0 C12 ormal lnput outp _ N0 V55 ormal NG _ 123 mnput outp _ orma YES N0 No ICl2 nput outpu YES 59 x orma _ vas W X ICHS x ICM x X Defective 99 ...

Page 102: ...putted at IC85 IC NO YES 95 X X 2 defect pen C C ICWS LIGHT PEN DOES NOT orrectly djusted YES lse ppear at JC 2 pln YES lse utputted at 25 11 p1 YES e outputted C18 9p1n YES Q cu x printer x WORK R mlssadj stment 12 NO 9 N0 _ 9 _ N0 S NO a I 1 X C X X Defective 100 ...

Page 103: ...n o NO YES l2v arm 2 No 200 No aveform Øs X 2 ly f f Sv alzwnorme D YES No ppl ntary wer norm 7 p _ to left No rans out t v rm _ T Tws YES 4 X Defective A5 3 IIIKUB A4 A2 efer power unit adjustment i from lef E t a e lead a TH13 output volta appe L YES 45 12v power YES waveform nm1 YES wus YES Cl00 X YES zumzum T Q X ra X on No ll 1 V NO 1 H 3o z 3o zz n C300 lC400 X X P N0 N0 I 1 NO justment ...

Page 104: ...a L JDDJ J llj Lu receiving operation check set colour monitor green monitor cassette recorder Printer light pen 2 PS 32C cable nsznccheck parent set Fig 12 l Connection 12 2 Operation check method Operation check consists of the items in Tablel2 1 The check procedure should be carried out according to the following instruction Table 12 1 Operation check content No 1 test item content program file...

Page 105: ...rFY MOTOR czlxs c ON OFF printer interface test of the data bus KY PR control line p speaker varible test by SPK C oscillating sound and sound VR light pen interface operation test of sig LP C line RS 232C interface sig receive sending RS2 C operation test IO3 ...

Page 106: ...RUN i i i i 9 2 B R b r E i F 4 7 f a n Qnge O ma c Us ra m ffe T ai umi mm JDTm K rbvt mocg reg S L _ J__lL f 1 5 P Qj_ y iv b 7n az PUES RETURN ke 1 G_yy g _ a 1 az an a LjlLXh x 47 lhU we YES 9l__Li Z il1 7__f__iQi f 1J 2 L 1 l V L K f f i f f _ fif fff M enera or _ I L 7 U J h I L 7 U J h g gg1 glVe Test 1 j Z s Eizf x Test 1 j Z s Eizf x R AD RUN _ _ _g __rg_j_ __ s l character ROM test On_ 4...

Page 107: ... is so on 221132 33 321 NO gr 3 O colour CK NG N c ange Pr k y YES CO O D 5 R E n m N k Y ve 3 ilgg Øircuit black red green yellow 3 t g d ptgw SSE blue magenta cyan white 1 e yes ima xxx msn me wx ws sw wiØflØl 32 H iifslfi ZKSESJI Q i saggy gggg Hi 32523 N211 EEN Wil i 1253 3Ii gggØØiogufnalgeg Back colour OK NG N ve S RAPHi Key while graph key is pressed press Ei Ke _f _ NO e Qispfgv ear on e s...

Page 108: ...Q Øw ower o a er Press keys QggghicMode BGR Cl NO co fl _ E S Ø Y ra hic e e ator f t g af YES Ø GC IVE of the p w a r sec on agaln Graphic Mode Test 2 Program name Press PFS key ZGR CZ 5 Ø i h Ø i h u e Qu it I To be continued 106 Screen of graphic mode test Graphic Mode Check 1 thicker UK turn power off close DIP Turn power on press PF1 PFS Grauhic Mode Check 2 ...

Page 109: ...c ect ne DK 1 assetts ve L Press For Sw d b c E E t 1 YES M Input SKIPF Return T e 0 t e _ My QS S f e o e ape e a 1 Z1 U U r J TEST press keys ter interface 0 Print out of printer interface Program nuns gera e acc r ln t HQcreen H Qcreen 1236557330 QBCDEFGHrJKLnuoPQRsruvwxvz _ _ _ 7 M171 7 7 T 7 1 x 1 EBV E112 t 1 t 13411 ma v J cz Tw ___ Onfl f mu rlnc gut correc f s V C l V YES X inpu key Scree...

Page 110: ...g Posh DFS key mh n_oolourchanges _ TP nn nnr11 l ranch DC 1 1 L T CHIC it L _ f _ L _ f _ l l K 1 l f gf t en YES e ect ve RS 232C _l_______________ 525C Cgxeg par m lnter face test g lne on gmm 39433 1 ss r keys _ Another me 6890 nnmwmnmumnw and key inPUt PreSS From MBGBQU H1 RET l23 REfl _ gazc Interface i f i f I I input Progr e ggeggrgggccor l 9 m Qutput on this me 6890 like mum _RS2_C 1ns ru...

Page 111: ...muumao nanfa1 1 0 aanuwamulan o s ru 300 FCR I 1T01O 310 BEEP 320 XTJ 330 END 340 PRINT 0 1 nm a1 autumnn u s 1 m4 m n un vmnw mu1m1 4 350 PRINT 1 DU K K U SSO PRINT U U 0 K K HRSK ROP I 370 PRINT WI O D KKK_ so Penn o o K x orl a T 390 PRINT 11 13 K K U A00 PRINT unnmuuasn versa uo n an aoannsw usecs an as funn A10 LDCQTE 0122 620 PRlNT l l j2 1 9 H RDP G f2 I 1 430 PRINT U j Ll I 1 7 i 2 Ø l F A...

Page 112: ... 7 u xNe c1oo xso sera Lncnre 0 20IPRINT f Locn1 so 22zr nx r ox ruafv Pnvvgg err cs asa 9 P S w r PRINT rogw Fav gf mv P z5 5 ffF P LDCRTE 0 23 5 GR432 graphic mode test 2 cz _ f s Lucn1 a s rnxr4r P P M905 5 2 14 20 30 50 LINEClO0 50 1500 ISOL PSE1 7 B LlNECl00 50 500 50 PSET T LINE 500 50 100 150 PSE v7 ______ _ __ ____ __ f _ _ ___ LUCHTE Uv ZOIFRINY rafvgg s R 1 1 v r a p g rapg 5 CAS C casse...

Page 113: ...O C CD1 lF CIA GOTO 900 ELSE 110 NEXT CLS LOCRTE CLS 0 X02 PRXNT lmwovm KE YGGHKO T567 extra 0 0 1 3 PRINT rr m m m 5 1 N P U 1 Pl L vm 3 P 1 f 7 7 1 o GK l LPT0l PRXNT lv PRlNTU1 P R I N T 1 LOCQTE LOCQTE O P E N O CLOSE X LOCRTE 0 H 12 h557B90 RBCDEFGHIJKLHNOPORSTUVHXYZ 74717 h 773 WDRUV YZIZI dt7NX TKL 11 P15 UU 771 IF Qi N GOTO 800 R U N S P K C CLS LUCQTE 0 10 PRINT LOCRTE 0 2O END CLS LDCRTE...

Page 114: ...HUIPRINT Qusw PF KEY IF vo cf fafvqi 290 D lPRINT W 1 1 300 ON KEY 5 GOSUB 510 310 U1 KEY 1 GOSUB 580 320 KEVCS GN 330 l Y 1 ON 340 PEN UN 350 GOTUZSO 350 KEY S OFF 370 KEYK1 TF 380 END 350 R91 00 RETURN 10 LINE 50 50 120 100 PSET 2 BF A20 RETURN 530 L1NE 150 50 220 100 PSET 5 BF 440 RETURN 50 L1NE 2S0 50 I20 100 PSET 4 BF 450 RETURN 70 L1NE 350 50 B20 100 PSET 5 BF 030 RETURN B90 LINE lL50 50 520...

Page 115: ...Lyme a fmfvrnez masvwo G P E N D 1 C O H 0 t SSN2 Fon J 1 TD B PR1NT6 1 12I S5S7B90 l NEXT PRINTII CLOSE 1 PRINT XNPUT OK IDS IF Q N GOTO B00 REr1 vw RS 232C INPUT XRD 1 5 T w w CLS Locnrs O 102PRINT Rs zszc mvur Rn rsw PRXNTIPRINT w Npur Pnmf PnmT n a c 1 2 3 MM Q f 5 M s r 1 o m g omg PR1NT PR1NT 71 f n5con Raavr Ra av r PRINT PRINT VN TP S A 6 0 1 f R 1 N T P R I N T PF 5 Kev F ck Pnmrsvaxnr 5 ...

Page 116: ... 6 Y n CH 300PU 2 oeooo 1 1 I w 1 Y v Ti TP 940 1 oeooo as mlm MB saso1ovooo MB saso 1 ovooo an Q pvev cn se 1 01320 1 dow 51 v 9f 1 o1ooo 1 as mph O Ø F MB ssso 1 ovooo dw C 0 V MB ssao 1 oswo A2 an JC1 L31 Hnsaos Mcssos Ma osso 1 00331 Al an xc wnzasac san 1 ovsso A6 as IC4 A Pn2as4c aa1 1 msn A6 1 rcs E 5 1 uPn23s4c 132 M11 saso 1 msc A7 xcs SN74LS245N MP 1010A 1 ossoo A3 lcv Hm4Lsas1A1 Ma saso...

Page 117: ... 02200 icss HD74LSl7 IP MB ease 05300 as 1c40 HD74LS283P MB 0090 01300 B6 1c41 L 5 1 HD74LS367AP Ma esac 04200 az cn HD74LSl64P oosoo B1 IC43 HD74S04P Ma saso 07100 A4 1044 HD74LS04P Maesso 06000 cz cas Hn141 s10P 06000 B3 IC46 L S L HD7 LS02P MB ssao 00000 B4 1011 1 HD74LSO0P 06000 1040 11m4Ls0sP MP asao 01100 A4 1 cas Ma 0090 01100 ca rcso _ 5 L HD74LS74AP HD HLS74AP 05000 B4 zcsn HD74LS157P MB ...

Page 118: ...1 s14A1 001 1 05000 A4 11 94 HD74LS02P MB 0000 005 1 00000 A2 1c95 1 1m41 s051 001 1 1 00000 B3 1c90 11m41 s0s1 MP 3530 013 1 01100 cs lC97 L S I I D74LS32P MB 6881 000 I 1 02100 Al as xcss HD74LSl2SAP MB 6890 025 1 07100 IC99 HD74LS74AP 001 1 05000 C4 IC100 HD74LS04P MB 0000 000 1 00000 A3 1c101 LS I HM4LS93P MP 3530 014 1 03200 aa ICIOZ 1 03200 C4 lCl03 HD74LS74AP HD74LS74AP 001 1 05000 IC104 HD...

Page 119: ...64200 Bl 1c141 L S I fHm4Ls151z Msissso ozz ozzoo D3 lCl42 HD 74LS02P MB 6880 oos oeooo IC143 1 mmLsosP 11P ssao ma ouoo D4 ICI44 l HD74LS32P 1MB 6881 oos ozxoo cus Hm41 sooP Ms ease oo4 osooo sz IC146 L SI HD74LSOSP MP asso 013 onoo D6 1c141 HD74LS1S7P Museo ozz ozzoo D5 gm un141 s1u 1 HD74LS74AP oo1 ossoo D4 Q1 t T 8 T 1 S i S t O 1 2 S C 4 5 8 oeooo ns Q2 ZSA673 ovooo Q3 zsc1z1afi 07000 B1 Q4 2...

Page 120: ... F101 fUS 1 sA sc 640 00000 fuse holdernox zpcs cn a001 u 06000 OWQI CO rd C18 227 08100 u S t C O ver as MP 1010A 00000 I pugh S W lgck MB 6890 01100 I 4 1 Pu Spj_11 TP 940 06000 an cOnnecto1 11Ug _16P MB 6090 01010 ns zsP 09720 as as Y e pm za P 04900 1 R4 04900 0 l IF1 Q0n q Jfu 56 P 09500 9 W2 095 ns 11 a f 00 09500 0 nf IF4 09500 9 an Ps 09500 0 nr Ps 09500 POWER UN I T cs an IC100 L 3 I MB 3...

Page 121: ...oo A6 ZD230 RDISEBI 137 1 1 o1ooo B3 ZD23l 2_ _y y ode lwasl az MB 6890 138 1 moo A6 znaao RDIIEBI X35 1 moo zmao 4 nnxasas 1 19 1 moo B3 ZD43I r nnzoem 140 1 moo A2 1111 Y f SJVZY sP2M Ma esso 143 1 oaaoo cs n x1ao oavosm MP aszo no 1 moo A2 A T1 Y f 5 J m 5 l f 4 E Y 1 11144 Ms eaao 101 1 o144o B3 A rs r o U l 4 F E 2 1 0 2 1 o m o U l4FE 2 102 1 omo ca A T4 A c rw 1 s MD sooo1011moo MD sooo 101...

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