Hitachi MB-6890, Service Manual

Page: 16 / 123

*
a
Low. Data
in
Output
Register
A
may
be read by
an
M?U
"Read
Peripheral
Data
A" operation when the corresponding
lines
are
programmed
as
outputs.
This data
will
be read properly
if the voltage
on
the
peripheral
data
lines
is
greater
than
2.0 volts for
a
logic l
output
and less
than
0.8
volt for
a
logic
0
output.
Loading the
output
lines such that the
voltage
on
these lines does not
reach full
voltage
causes
the data
transferred
into
the MPU
on a
Read operation to differ from that
contained
in
the respective
bit of
Output
Register
A.
Section
B
Peripheral Data
(PBSPB7)
The peripheral data
lines
on
the
B
Section of the PIA
can
be programmed
to act
as
either
inputs
or
outputs
on a
similar
manner
to
P A P A 7 .
However,
the output
buffers driving these
lines differ from
Qhose
driving
lines
P A 5 P A 7 .
They
have three
state
capability,allowing
them
to enter
a
high impedance
state
when the peripheral
data line is used
as a
input.
In
addition, data
on
the
peripheral
data lines
PB6»PB7
will
be read
properly from
those lines
programmed
as
outputs.
As
outputs,
these
lines
are
compatible
with
standard TTL and
may
also be used
as a
source
of
up
to
2.5 milliampere(typ.)
at
1.5 volts to directly
drive
the
base of
a
transistor switch.
*
Interrupt Input(CA1andCB1)
Peripheral Input
lines
CAl
and
CA2 are
input
only
lines
that set
the
interrupt
flag
of the control registers,
The active transition for these
signals
is
also programmed by
the
two
control registers.
* Peripheral
Control
(te2)
TheD91‘iDh91‘controllineCAcanbeprogrammedtoactasan
control
line
CA
can
be
programmed to act
as an
interrupt input
or
asa
D9fiDh9%5l
control
output.
As
an
output,
this
line is
compatible
with standard TTL. The
function
of
this
signal
line
is
programmed
with Control Register A.
*
Peripheral
Control(CB2)
Peripheral
COntrol line
CB2 may
also be programmed to act
as
an
inter-
rupt
input
or
peripheral control
output.
As
an
input,this
line has
High
input impedance and
is
compatible
with standard
TTL. As
an
output
it
is compatible
with
standard TTL
and
may
also be used of
up
to
2.5 mill-
iampere(typ.) at
1.5 volts
to
directly drive the base of
a
transistor
switch. This line is controlled
by
Control Register B.
(ACIA
3
Asynchronous Communication
Interface Adapter)
W) Pin
arrangement
(GND)
Vss
Rx Dafa
RICLK
TxCLK
EE
Tx Dau
EE
Gm
as
(31
M
(5V)V¢c
2
7
HD4685OP
MCM)
2;
23
E5
E5
Do
D1
D7
DJ
D4
Ds
D7
/W
||
||
ll
|$
EE
El
E5
||
I5
El
Ds
IE
@
~
E
R
SIGNAL FUNCTION
*
Interface
Signal for MPU
*
Bi- Directional
Data
Bus(DO\D7)
The bi-directional data
bus(DOf
D7)
allow for
data transfer
between the
ACTA and
the
MPU.
The data bus
output
drivers
are
three
state
devices that in the
high impedance(off)
state
;xC9Dt
when
the MPU
perform
an
ACIA
YDZA nnnrnØ-inn
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