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Hitachi H8/3670F-ZTAT HD64F3670, Hardware Manual

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Hitachi H8/3670F-ZTAT HD64F3670 Hardware Manual Download Page 168

Rev. 1.0, 03/01, page 144 of 280

11.5.4

Timing of Counter Clearing by Compare Match

Figure 11-18 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N

+

1.

TCNT

Compare 
match signal

φ

GRA

N

N

H'0000

Figure 11-18   Timing of Counter Clearing by Compare Match

11.5.5

Buffer Operation Timing

Figures 11-19 and 12-20 show the buffer operation timing.

GRC, GRD

Compare 
match signal

TCNT

φ

GRA, GRB

N

N+1

M

M

Figure 11-19   Buffer Operation Timing (Compare Match)

Summary of Contents for H8/3670F-ZTAT HD64F3670

Page 1: ...Hitachi Single Chip Microcomputer H8 3672 Series H8 3672F ZTATTM HD64F3672 H8 3670F ZTATTM HD64F3670 Hardware Manual ADE 602 239 Rev 1 0 03 20 01 Hitachi Ltd ...

Page 2: ...Rev 2 0 03 01 page ii of xxiv ...

Page 3: ...e or cause risk of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other char...

Page 4: ...Rev 2 0 03 01 page iv of xxiv ...

Page 5: ...cted to understand the fundamentals of electrical circuits logical circuits and microcomputers Objective This manual was written to explain the hardware functions and electrical characteristics of the H8 3672 Series to the above audience Refer to the H8 300H Series Programming Manual for a detailed description of the instruction set Notes on reading this manual In order to understand the overall f...

Page 6: ...al H8 300H Series Programming Manual ADE 602 053 Users manuals for development tools Manual Title ADE No C C Compiler Assembler Optimized Linkage Editor User s Manual ADE 702 246 Hitachi Debugging Interface User s Manual ADE 702 212 Hitachi Embedded Workshop User s Manual ADE 702 201 Hitachi Embedded Workshop Hitachi Debugging Interface Tutorial ADE 702 231 F ZTAT Microcomputer On Board Writing Pr...

Page 7: ... Modes and Effective Address Calculation 27 2 5 1 Addressing Modes 27 2 5 2 Effective Address Calculation 29 2 6 Basic Bus Cycle 32 2 6 1 Access to On Chip Memory RAM ROM 32 2 6 2 On Chip Peripheral Modules 33 2 7 CPU States 34 2 8 Usage Notes 35 2 8 1 Notes on Data Access to Empty Areas 35 2 8 2 EEPMOV Instruction 35 2 8 3 Bit Manipulation Instruction 35 Section 3 Exception Handling 41 3 1 Except...

Page 8: ...Pulse Generators 61 5 1 System Clock Generator 61 5 1 1 Connecting a Crystal Oscillator 61 5 1 2 Connecting a Ceramic Oscillator 62 5 1 3 External Clock Input Method 62 5 2 Prescalers 63 5 2 1 Prescaler S 63 5 3 Usage Notes 63 5 3 1 Note on Oscillators 63 5 3 2 Notes on Board Design 64 Section 6 Power down Modes 65 6 1 Register Descriptions 65 6 1 1 System Control Register 1 SYSCR1 65 6 1 2 System...

Page 9: ...ware Protection 86 7 5 2 Software Protection 86 7 5 3 Error Protection 86 Section 8 RAM 87 Section 9 I O Ports 89 9 1 Port 1 89 9 1 1 Port Mode Register 1 PMR1 90 9 1 2 Port Control Register 1 PCR1 91 9 1 3 Port Data Register 1 PDR1 91 9 1 4 Port Pull Up Control Register 1 PUCR1 92 9 1 5 Pin Functions 92 9 2 Port 2 94 9 2 1 Port Control Register 2 PCR2 94 9 2 2 Port Data Register 2 PDR2 95 9 2 3 P...

Page 10: ...Width and Delay from TRGV Input 120 10 6 Usage Notes 121 Section 11 Timer W 123 11 1 Features 123 11 2 Input Output Pins 125 11 3 Register Descriptions 126 11 3 1 Timer Mode Register W TMRW 126 11 3 2 Timer Control Register W TCRW 128 11 3 3 Timer Interrupt Enable Register W TIERW 129 11 3 4 Timer Status Register W TSRW 129 11 3 5 Timer I O Control Register 0 TIOR0 131 11 3 6 Timer I O Control Reg...

Page 11: ...al Control Register 3 SCR3 158 13 3 7 Serial Status Register SSR 160 13 3 8 Bit Rate Register BRR 162 13 4 Operation in Asynchronous Mode 167 13 4 1 Clock 168 13 4 2 SCI3 Initialization 169 13 4 3 Data Transmission 170 13 4 4 Serial Data Reception 172 13 5 Operation in Clocked Synchronous Mode 176 13 5 1 Clock 176 13 5 2 SCI3 Initialization 176 13 5 3 Serial Data Transmission 177 13 5 4 Serial Dat...

Page 12: ...es on Absolute Precision 203 Section 15 Power Supply Circuit 205 15 1 When Using the Internal Power Supply Step Down Circuit 205 15 2 When Not Using the Internal Power Supply Step Down Circuit 206 Section 16 Electrical Characteristics 207 16 1 Absolute Maximum Ratings 207 16 2 Electrical Characteristics 207 16 2 1 Power Supply Voltage and Operating Ranges 207 16 2 2 DC Characteristics 209 16 2 3 A...

Page 13: ...egister Bits 254 B 3 Registers States in Each Operating Mode 257 Appendix C I O Port Block Diagrams 260 C 1 I O Port Block 260 C 2 Port States in Each Operating State 275 Appendix D Product Code Lineup 276 Appendix E Package Dimensions 277 ...

Page 14: ...Rev 2 0 03 01 page xiv of xxiv ...

Page 15: ...on States 34 Figure 2 12 State Transitions 35 Figure 2 13 Example of Timer Configuration with Two Registers Allocated to Same Address 36 Section 3 Exception Handling Figure 3 1 Reset Sequence 49 Figure 3 2 Stack Status after Exception Handling 50 Figure 3 3 Interrupt Sequence 52 Figure 3 4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure 53 Section 4 Address Break Figure 4 ...

Page 16: ...igure 10 3 Increment Timing with External Clock 116 Figure 10 4 OVF Set Timing 117 Figure 10 5 CMFA and CMFB Set Timing 117 Figure 10 6 TMOV Output Timing 117 Figure 10 7 Clear Timing by Compare Match 117 Figure 10 8 Clear Timing by TMRIV Input 118 Figure 10 9 Pulse Output Example 119 Figure 10 10 Example of Pulse Output Synchronized to TRGV Input 120 Figure 10 11 Contention between TCNTV Write an...

Page 17: ...ion 148 Section 12 Watchdog Timer Figure 12 1 Block Diagram of WDT 149 Figure 12 2 Watchdog Timer Operation Example 152 Section 13 Serial Communication Interface3 SCI3 Figure 13 1 Block Diagram of SCI3 154 Figure 13 2 Data Format in Asynchronous Communication 167 Figure 13 3 Relationship between Output Clock and Transfer Data Phase Asynchronous Mode Example with 8 Bit Data Parity Two Stop Bits 168...

Page 18: ...igure 14 5 A D Conversion Precision Definitions 2 203 Figure 14 6 Analog Input Circuit Example 204 Section 15 Power Supply Circuit Figure 15 1 Power Supply Connection when Internal Step Down Circuit Is Used 205 Figure 15 2 Power Supply Connection when Internal Step Down Circuit Is Not Used 206 Section 16 Electrical Characteristics Figure 16 1 System Clock Input Timing 221 Figure 16 2 RES Low Width...

Page 19: ... 13 Port 7 Block Diagram P74 272 Figure C 14 Port 8 Block Diagram P84 to P81 273 Figure C 15 Port 8 Block Diagram P80 274 Figure C 16 Port B Block Diagram PB3 to PB0 275 Appendix E Package Dimensions Figure E 1 FP 64E Package Dimensions 277 Figure E 2 FP 48F Package Dimensions 278 ...

Page 20: ...Rev 1 0 03 01 page xx of xxiv ...

Page 21: ...nsfer Instructions 25 Table 2 10 Addressing Modes 27 Table 2 11 Absolute Address Access Ranges 28 Table 2 12 Effective Address Calculation 1 30 Table 2 12 Effective Address Calculation 2 31 Section 3 Exception Handling Table 3 1 Exception Sources and Vector Address 42 Table 3 2 Interrupt Wait States 51 Section 4 Address Break Table 4 1 Access and Data Bus Used 57 Section 5 Clock Pulse Generators T...

Page 22: ...ious Bit Rates Asynchronous Mode 3 165 Table 13 3 Maximum Bit Rate for Each Frequency Asynchronous Mode 165 Table 13 4 BRR Settings for Various Bit Rates Clocked Synchronous Mode 166 Table 13 5 SSR Status Flags and Receive Data Handling 173 Table 13 6 SCI3 Interrupt Requests 190 Section 14 A D Converter Table 14 1 Pin Configuration 195 Table 14 2 Analog Input Channels and Corresponding ADDR Regist...

Page 23: ...ge xxiii of xxiv Table A 2 Operation Code Map 3 242 Table A 3 Number of Cycles in Each Instruction 244 Table A 4 Number of Cycles in Each Instruction 245 Table A 5 Combinations of Instructions and Addressing Modes 250 ...

Page 24: ...Rev 1 0 03 01 page xxiv of xxiv ...

Page 25: ... timer Watchdog timer SCI3 Asynchronous or clocked synchronous serial communication interface 10 bit A D converter On chip memory ROM Model ROM RAM F ZTAT Version HD64F3672 16k 2 048 bytes HD64F3670 8k 2 048 bytes General I O ports I O pins 26 I O pins including 5 large current ports IOL 20mA VOL 1 5V Input only pins 4 input pins also used for analog input Supports various power down states Compac...

Page 26: ...XD P21 RXD P20 SCK3 P84 FTIOD P83 FTIOC P82 FTIOB P81 FTIOA P80 FTCI P76 TMOV P75 TMCIV P74 TMRIV EIOT_0 EIOT_1 EIOT_2 OSC1 OSC2 Port 1 Data bus upper CPU H8 300H ROM RAM Data bus lower Timer W SCI3 Watchdog timer Timer V A D converter Port B CMOS large current port I OL 20 mA V OL 1 5 V System clock generator Port 2 Port 5 Address bus Port 7 Port 8 Figure 1 1 Internal Block Diagram ...

Page 27: ...RXD P20 SCK3 EIOT_2 EIOT_1 EIOT_0 P84 FTIOD P83 FTIOC P82 FTIOB P81 FTIOA P80 FTCI NC NC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC P14 P15 P16 P17 TRGV NC NC NC NC PB3 AN3 PB2 AN2 PB1 AN1 PB0 AN0 NC NC NC NC P76 TMOV P75 TMCIV P74 TMRIV P57 P56 P12 P11 P10 P55 P54 P53 P52 NC NC H8 3672 Top view Note Do not connect NC pins Figure 1 2 Pin A...

Page 28: ...TXD P21 RXD P20 SCK3 EIOT_2 EIOT_1 EIOT_0 P84 FTIOD P83 FTIOC P82 FTIOB P81 FTIOA P80 FTCI 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 P14 P15 P16 P17 TRGV NC NC NC NC PB3 AN3 PB2 AN2 PB1 AN1 PB0 AN0 P76 TMOV P75 TMCIV P74 TMRIV P57 P56 P12 P11 P10 P55 P54 P53 P52 H8 3672 Top view Figure 1 3 Pin Arrangement FP 48F ...

Page 29: ...is pin and the Vss pin for stabilization Clock pins OSC1 11 9 Input OSC2 10 8 Output These pins connect to a crystal or ceramic oscillator for system clocks or can be used to input an external clock These pins can be used to input an external clock See section 5 Clock Pulse Generators for a typical connection System control RES 7 5 Input Reset pin When this driven low the chip is reset TEST 8 6 In...

Page 30: ... 33 I O Interface pin for EIOT emulator Serial com munication TXD 46 36 Output Transmit data output pin interface SCI RXD 45 35 Input Receive data input pin SCK3 44 34 Output Clock I O pin A D converter AN3 to AN0 59 to 62 45 to 48 Input Analog input pin ADTRG 22 16 Input A D converter trigger input pin I O ports PB3 to PB0 59 to 62 45 to 48 Input 4 bit input port P17 to P14 P12 to P10 54 to 51 25...

Page 31: ... and arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 24 ERn Register indirect with post increment or pre decrement ERn or ERn Absolute address aa 8 aa 16 aa 24 Immediate xx 8 xx 16 or xx 32 Program counter relative d 8 PC or d 1...

Page 32: ...OT Internal I O register H 0000 H 0033 H 0034 H 3FFF H 4000 H 4FFF EIOT control program area 4 kbytes H 4000 H 4FFF H F780 H FB7F H FF7F H FF80 H FB80 H F780 H FB7F H FB80 H FFFF HD64F3672 Flash memory version HD64F3670 Flash memory version Interrupt vector On chip ROM 8 kbytes Not used Not used H 0000 H 0033 H 0034 H FF7F H FF80 H FFFF H 1FFF 1 kbyte user area On chip RAM 2 kbytes 1 kbyte work ar...

Page 33: ...dition code register CCR PC 23 0 15 0 7 0 7 0 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC CCR I UI Stack pointer Program counter Condition code register Interrupt mask bit User bit Half carry flag User bit Negative flag Zero flag Overflow flag Carry flag ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 SP I UI H U N Z V C CCR 7 6 5 4 3 2 1 0 H U N Z V C General Reg...

Page 34: ...rs are functionally equivalent providing a maximum of sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum of sixteen 8 bit registers The usage of each register can be selected independently Gen...

Page 35: ...tor address generated during reset exception handling sequence 2 2 3 Condition Code Register CCR This 8 bit register contains internal CPU status information including an interrupt mask bit I and half carry H negative N zero Z overflow V and carry C flags The I bit is initialized to 1 by reset exception handling sequence but other bits are not initialized Some instructions leave flag bits unchange...

Page 36: ...d cleared to 0 otherwise When the ADD L SUB L CMP L or NEG L instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 27 and cleared to 0 otherwise 4 U undefined R W User Bit Can be written and read by software using the LDC STC ANDC ORC and XORC instructions 3 N undefined R W Negative Flag Stores the value of the most significant bit of data as a sign bit 2 Z undefined ...

Page 37: ...treat byte data as two digits of 4 bit BCD data 2 3 1 General Register Data Formats Figure 2 5 shows the data formats in general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care Don t care Don t care 7 0 4 3 7 0 Don t care 6 5 4 3 2 7 1 0 7 0 Don t care 6 5 4 3 2 7 1 0 Don t care RnH RnL RnH RnL RnH RnL Data Type General Register Data Format Byte data Byte data 4 bit BCD data 4 bit BCD data 1 ...

Page 38: ...H RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Format General Register Word data Word data Rn En Longword data Legend ERn Figure 2 5 General Register Data Formats 2 ...

Page 39: ...r does not occur however the least significant bit of the address is regarded as 0 so access begins the preceding address This also applies to instruction fetches When ER7 SP is used as an address register to access the stack the operand size should be word or longword 7 0 7 6 5 4 3 2 1 0 MSB LSB MSB MSB LSB LSB Data Type Address 1 bit data Byte data Word data Address L Address L Address 2M Addres...

Page 40: ...er ERn General register 32 bit register or address register EAd Destination operand EAs Source operand CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT logical comple...

Page 41: ... a general register MOVFPE B EAs Rd Cannot be used in this LSI MOVTPE B Rs EAs Cannot be used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP PUSH L ERn is identical to MOV L ERn SP Note Refers to the operand size...

Page 42: ...n be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general registers either 8 b...

Page 43: ...egister or with immediate data and sets CCR bits according to the result NEG B W L 0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower ...

Page 44: ...on a general register and another general register or immediate data NOT B W L Rd Rd Takes the one s complement of general register contents Note Refers to the operand size B Byte W Word L Longword Table 2 5 Shift Instructions Instruction Size Function SHAL SHAR B W L Rd shift Rd Performs an arithmetic shift on general register contents SHLL SHLR B W L Rd shift Rd Performs a logical shift on gener...

Page 45: ...ral register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND B B C bit No of EAd C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C bit No of EAd C ANDs the carry flag with the inverse of a specified bit i...

Page 46: ...by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BST BIST B B C bit No of EAd Transfers the carry flag value to a specified bit in a general regi...

Page 47: ... High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified addres...

Page 48: ...fer from memory data is read by word access STC B W CCR EAd EXR EAd Transfers the CCR contents to a destination location The condition code register size is one byte but in transfer to memory data is written by word access ANDC B CCR IMM CCR EXR IMM EXR Logically ANDs the CCR with immediate data ORC B CCR IMM CCR EXR IMM EXR Logically ORs the CCR with immediate data XORC B CCR IMM CCR EXR IMM EXR ...

Page 49: ...the address set in ER5 transfers data for the number of bytes set in R4L or R4 to the address location set in ER6 Execution of the next instruction begins as soon as the transfer is completed 2 4 2 Basic Instruction Formats H8 300H CPU instructions consist of 2 byte 1 word units An instruction consists of an operation field op field a register field r field an effective address extension EA field ...

Page 50: ...ster fields Some have no register field Effective Address Extension 8 16 or 32 bits specifying immediate data an absolute address or a displacement A24 bit address or displacement is treated as a 32 bit data in which the first 8 bits are 0 H 00 Condition Field Specifies the branching condition of Bcc instructions op op rn rm NOP RTS etc ADD B Rn Rm etc MOV B d 16 Rn Rm rn rm op EA disp op cc EA di...

Page 51: ...bsolute addressing mode to specify an operand and register direct BSET BCLR BNOT and BTST instructions or immediate 3 bit addressing mode to specify a bit number in the operand Table 2 10 Addressing Modes No Addressing Mode Symbol 1 Register direct Rn 2 Register indirect ERn 3 Register indirect with displacement d 16 ERn d 24 ERn 4 Register indirect with post increment Register indirect with pre d...

Page 52: ...address register ERn specified by the register field in the instruction code and the lower 24 bits of the result is the address of a memory operand The result is also stored in the address register The value subtracted is 1 for byte access 2 for word access or 4 for longword access For the word or longword access the register value should be even Absolute Address aa 8 aa 16 aa 24 The instruction c...

Page 53: ...n The resulting value should be an even number Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The instruction code contains an 8 bit absolute address specifying a memory operand This memory operand contains a branch address The memory operand is accessed by longword access The first byte of the memory operand is ignored generating a 24 bit branch address Figure 2 8 show...

Page 54: ...tion Effective Address EA Register direct Rn General register contents General register contents General register contents General register contents Sign extension Register indirect ERn Register indirect with post increment or pre decrement Register indirect with post increment ERn Register indirect with pre decrement ERn 1 2 or 4 1 2 or 4 Operand is general register contents The value to be added...

Page 55: ...t Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 7 Program counter relative d 8 PC d 16 PC Memory indirect aa 8 23 0 disp 0 23 0 disp op 23 op 8 abs 23 0 abs H 0000 7 8 0 15 23 0 15 H 00 16 Legend r rm rn op disp IMM abs Register field Operation field Displacement Immediate data Absolute address PC contents Sign extension Memo...

Page 56: ...ccess is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Access to on chip memory takes place in two states The data bus width is 16 bits allowing access in byte or word size Figure 2 9 shows the on chip memory access cycle T1 state Bus cycle T2 state Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Ad...

Page 57: ...8 bit data bus width can be accessed by byte or word size When a register with 8 bit data bus width is accessed by word size access is completed in two cycles In two state access the operation timing is the same as that for on chip memory Figure 2 10 shows the operation timing in the case of three state access to an on chip peripheral module T1 state Bus cycle Internal address bus Internal read si...

Page 58: ... For details on exception processing refer to section 3 Exception Handling CPU state Reset state Program execution state Program halt state Exception handling state Active high speed mode Sleep mode Power down modes The CPU executes successive program instructions at high speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by the su...

Page 59: ... transfers the byte size of data indicated by R4L which starts from the address indicated by R5 to the address indicated by R6 Set R4L and R6 so that the end address of the destination address value of R6 R4L does not exceed H FFFF the value of R6 must not change from H FFFF to H 0000 during execution 2 8 3 Bit Manipulation Instruction The BSET BCLR BNOT BST and BIST instructions read data from th...

Page 60: ...er The timer is counting so the value read is not necessarily the same as the value in the timer load register As a result bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register Read Write Count clock Timer counter Timer load register Reload Internal bus Figure 2 13 Example of Timer Configuration with Two Registers All...

Page 61: ...R5 0 1 0 0 0 0 0 1 Description on operation When the BSET instruction is executed first the CPU reads port 5 Since P57 and P56 are input pins the CPU reads the pin states low level and high level input P55 to P50 are output pins so the CPU reads the value in PDR5 In this example PDR5 has a value of H 80 but the value read by the CPU is H 40 Next the CPU sets bit 0 of the read data to 1 changing th...

Page 62: ...R0L MOV B R0L PDR5 The work area RAM0 value is written to PDR5 P57 P56 P55 P54 P53 P52 P51 P50 Input output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 1 RAM0 1 0 0 0 0 0 0 1 Bit Manipulation in a Register Containing a Write Only Bit Example 3 BCLR instructi...

Page 63: ... Low level Low level High level PCR5 1 1 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 Description on operation When the BCLR instruction is executed first the CPU reads PCR5 Since PCR5 is a write only register the CPU reads a value of H FF even though the PCR5 value is actually H 3F Next the CPU clears bit 0 in the read data to 0 changing the data to H FE Finally H FE is written to PCR5 and BCLR instruction e...

Page 64: ...Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 1 BCLR instruction executed BCLR 0 RAM0 The BCLR instructions executed for the PCR5 work area RAM0 After executing BCLR MOV B RAM0 R0L MOV B R0L PCR5 The work area RAM0 value is written to PCR5 P57 P56 P55 P54 P53 P52 P51 P50 Input output Input Input Output Output Output Output Output Output Pin state Low le...

Page 65: ...struction generates a vector address corresponding to a vector number from 0 to 3 as specified in the instruction code Exception handling can be executed at all times in the program execution state Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR and kept masked while the I bit is set to 1 Exception handling starts when t...

Page 66: ... by executing the SLEEP instruction 13 H 001A to H 001B IRQ0 14 H 001C to H 001D IRQ3 17 H 0022 to H 0023 WKP 18 H 0024 to H 0025 Reserved for system use 20 H 0028 to H 0029 Timer W Input capture A compare match A Input capture B compare match B Input capture C compare match C Input capture D compare match D Timer W overflow 21 H 002A to H 002B Timer V Timer V compare match A Timer V compare match...

Page 67: ... IEGR1 selects the direction of an edge that generates interrupt requests of pins and IRQ3 and IRQ0 Bit Bit Name Initial Value R W Description 7 0 Reserved This bit is always read as 0 and cannot be modified 6 5 4 1 1 1 Reserved These bits are always read as 1 and cannot be modified 3 IEG3 0 R W IRQ3 Edge Select 0 Falling edge of IRQ3 pin input is detected 1 Rising edge of IRQ3 pin input is detect...

Page 68: ...put is detected 4 WPEG4 0 R W WKP4 Edge Select 0 Falling edge of WKP4 pin input is detected 1 Rising edge of WKP4 pin input is detected 3 WPEG3 0 R W WKP3 Edge Select 0 Falling edge of WKP3 pin input is detected 1 Rising edge of WKP3 pin input is detected 2 WPEG2 0 R W WKP2 Edge Select 0 Falling edge of WKP2 pin input is detected 1 Rising edge of WKP2 pin input is detected 1 WPEG1 0 R W WKP1Edge S...

Page 69: ...cannot be modified 3 IEN3 0 R W IRQ3 Interrupt Enable When this bit is set to 1 interrupt requests of the IRQ3 pin are enabled 2 0 Reserved This bit is always read as 0 and cannot be modified 1 0 Reserved This bit is always read as 0 and cannot be modified 0 IEN0 0 R W IRQ0 Interrupt Enable When this bit is set to 1 interrupt requests of the IRQ0 pin are enabled When disabling interrupts by cleari...

Page 70: ... is always read as 0 and cannot be modified 5 4 1 1 Reserved These bits are always read as 1 and cannot be modified 3 IRRI3 0 R W IRQ3 Interrupt Request Flag Setting condition When IRQ3 pin is designated for interrupt input and the designated signal edge is detected Clearing condition When IRRI3 is cleared by writing 0 2 0 Reserved This bit is always read as 0 and cannot be modified 1 0 Reserved T...

Page 71: ...s cleared by writing 0 3 IWPF3 0 R W WKP3 Interrupt Request Flag Setting condition When WKP3 pin is designated for interrupt input and the designated signal edge is detected Clearing condition When IWPF3 is cleared by writing 0 2 IWPF2 0 R W WKP2 Interrupt Request Flag Setting condition When WKP2 pin is designated for interrupt input and the designated signal edge is detected Clearing condition Wh...

Page 72: ...n that address is sent to the program counter PC as the start address and program execution starts from that address 3 4 Interrupt Exception Handling 3 4 1 External Interrupts There are external interrupts NMI IRQ3 IRQ0 and WKP NMI NMI interrupt is requested by input falling edge to pin NMI NMI is the highest interrupt and can always be accepted without depending on the I bit value in CCR IRQ3 to ...

Page 73: ...al write signal Internal data bus 16 bits Internal processing Initial program instruction prefetch 1 Reset exception handling vector address H 0000 2 Program start address 3 Initial program instruction 2 3 2 1 Reset cleared Figure 3 1 Reset Sequence 3 4 2 Internal Interrupts Each on chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the i...

Page 74: ...rupt after processing of the current instruction is completed interrupt exception handling will begin First both PC and CCR are pushed onto the stack The state of the stack at this time is shown in figure 3 2 The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling 5 Then the I bit of CCR is set to 1 masking further interrupts ex...

Page 75: ...errupt handling routine Register contents must always be saved and restored by word length starting from an even numbered address 3 Ignored when returning from the interrupt handling routine Figure 3 2 Stack Status after Exception Handling 3 4 4 Interrupt Response Time Table 3 2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt hand...

Page 76: ...uted Address is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector address 9 Starting address of interrupt handling routine contents of vector 10 First instruction of interrupt handling routine 3 9 8 6 5 4 1 7 10 Stack access Internal processing Instruction prefetch Interrupt level d...

Page 77: ...tore register values 3 5 3 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins IRQ3 to IRQ0 and WKP5 to WKP0 the interrupt request flag may be set to 1 Figure 3 4 shows a port mode register setting and interrupt request flag clearing procedure When switching a pin function mask the interrupt before setting the bit in the ...

Page 78: ...Rev 1 0 03 01 page 54 of 280 ...

Page 79: ...orrecting program Figure 4 1 shows a block diagram of the address break BARH BARL BDRH BDRL ABRKCR ABRKSR Internal address bus Comparator Interrupt generation control circuit Internal data bus Comparator Interrupt Legend BARH BARL Break address register BDRH BDRL Break data register ABRKCR Address break control register ABRKSR Address break status register Figure 4 1 Block Diagram of an Address Br...

Page 80: ...address bus 000 Compares 16 bit addresses 001 Compares upper 12 bit addresses 010 Compares upper 8 bit addresses 011 Compares upper 4 bit addresses 1XX Reserved 1 0 DCMP1 DCMP0 0 0 R W R W Data Compare Condition Select 1 and 0 These bits set the comparison condition between the data set in BDR and the internal data bus 00 No data comparison 01 Compares lower 8 bit data between BDRL and data bus 10...

Page 81: ... interrupt enable bit Bit Bit Name Initial Value R W Description 7 ABIF 0 R W Address Break Interrupt Flag Setting condition When the condition set in ABRKCR is satisfied Clearing condition When 0 is written after ABIF 1 is read 6 ABIE 0 R W Address Break Interrupt Enable When this bit is 1 an address break interrupt request is enabled 5 4 3 2 1 0 0 0 0 0 0 0 Reserved These bits are always read as...

Page 82: ...nation of the address set in BAR the data set in BDR and the conditions set in ABRKCR the address break function generates an interrupt request to the CPU When the interrupt request is accepted interrupt exception handling starts after the instruction being executed ends The address break interrupt is not masked because of the I bit in CCR of the CPU Figures 4 2 show the operation examples of the ...

Page 83: ...rupt request 025E 0260 025A 0262 0264 SP 2 MOV instruc tion 2 prefetch NOP instruc tion prefetch MOV instruc tion execution Next instru ction prefetch Internal processing Stack save NOP instruc tion prefetch Interrupt acceptance Underline indicates the address to be stacked When the address break is specified in the data read cycle Figure 4 2 Address Break Interrupt Operation Example 2 ...

Page 84: ... 2 prefetch NOP instruc tion prefetch Stack resumption Internal processing MOV instruc tion execution 025A Interrupt acceptance 0262 SP 2 SP 4 XXXX NOP instruc tion prefetch Vector fetch Internal processing Stack restore Internal processing 039A 039C 039E NOP RTE NOP Interrupt Interrupt Underline indicates the address to be stacked When the interrupt acceptance is prohibited after the RTE RTB inst...

Page 85: ...f Clock Pulse Generators The basic clock signals that drive the CPU and on chip peripheral modules are ø The system clock is divided into ø 8192 to ø 2 by prescaler S and they are supplied to respective peripheral modules 5 1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator or by providing external clock input 5 1 ...

Page 86: ...amic Oscillator Figure 5 4 shows a typical method of connecting a ceramic oscillator OSC1 OSC2 C1 C2 C1 30 pF 10 C2 30 pF 10 Figure 5 4 Typical Connection to Ceramic Oscillator 5 1 3 External Clock Input Method Connect an external clock signal to pin OSC1 and leave pin OSC2 open Figure 5 5 shows a typical connection The duty cycle of the external clock signal must be 45 to 55 OSC1 External clock i...

Page 87: ...ratio can be set separately for each on chip peripheral function In active mode the clock input to prescaler S is determined by the division factor designated by MA2 and MA0 in SYSCR2 5 3 Usage Notes 5 3 1 Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user referring to the examples shown in this section Oscillator circui...

Page 88: ...he resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation see figure 5 6 OSC1 OSC2 C1 C2 Signal A Signal B Avoid Figure 5 6 Example of Incorrect Board Design ...

Page 89: ...Standby mode The CPU and all on chip peripheral modules halt Subsleep mode The CPU and all on chip peripheral modules halt I O ports keep the same states as before the transition Module standby mode Independent of the above modes power dissipation can be reduced by halting on chip modules that are not used in module units 6 1 Register Descriptions The registers related to power down modes are list...

Page 90: ... the specified value and the number of wait states is shown in table 6 1 When an external clock is to be used the minimum value STS2 STS1 STS0 1 is recommended 3to0 0 Reserved These bits are always read as 0 and cannot be modified Table 6 1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0 5 MHz 0 0 0 8 192 states 0 5 0 8 1 0 2 0 4 1 8 1 16 4 ...

Page 91: ...of a SLEEP instruction as well as bit SSBY of SYSCR1 For details see table 6 2 4 3 2 MA2 MA1 MA0 0 0 0 R W R W R W Active Mode Clock Select 2 to 0 These bits select the operating clock frequency in the active and sleep modes The operating clock frequency changes to the set frequency after the SLEEP instruction is executed 0XX φOSC 100 φOSC 8 101 φOSC 16 110 φOSC 32 111 φOSC 64 1 0 0 0 Reserved The...

Page 92: ...e internal oscillator is selected for the watchdog timer clock the watchdog timer operates regardless of the setting of this bit 2 MSTTW 0 R W Timer W Module Standby Timer W enters the standby mode when this bit is set to 1 1 MSTTV 0 R W Timer V Module Standby Timer V enters the standby mode when this bit is set to 1 0 0 Reserved This bit is always read as 0 and cannot be modified 6 1 4 Module Sta...

Page 93: ...on directly from active mode to active mode and from subactive mode to subactive mode RES input enables transitions from a mode to the reset state Table 6 2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt Table 6 3 shows the internal states of the LSI in each mode Reset state Standby mode Active mode Sleep mode Subsleep mode...

Page 94: ...de System clock oscillator Functioning Functioning Halted Halted Instructions Functioning Halted Halted Halted CPU operations Registers Functioning Retained Retained Retained RAM Functioning Retained Retained Retained IO ports Functioning Retained Retained Register contents are retained but output is the high impedance state IRQ3 IRQ0 Functioning Functioning Functioning Functioning External interr...

Page 95: ...k pulse generator starts After the time set in bits STS2 STS0 in SYSCR1 has elapsed and interrupt exception handling starts The standby mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register When the RES pin goes low the system clock pulse generator starts Since system clock signals are supplied to the entire chip as soon as the ...

Page 96: ...ion in the active mode After the mode transition direct transition interrupt exception handling starts If the direct transition interrupt is disabled in interrupt enable register 1 a transition is made instead to the sleep mode Note that if a direct transition is attempted while the I bit in CCR is set to 1 the sleep mode will be entered and the resulting mode cannot be cleared by means of an inte...

Page 97: ... entire flash memory In normal user program mode individual blocks can be erased or programmed Automatic bit rate adjustment For data transfer in boot mode this LSI s bit rate can be automatically adjusted to match the transfer bit rate of the host Programming erasing protection Sets software protection against flash memory programming erasing Power down mode The power supply circuit is partly hal...

Page 98: ...FFF H 4F80 H 4F81 H 4F82 Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes 1kbyte Erase unit 1kbyte Erase unit 1kbyte Erase unit 1kbyte Erase unit 16 kbytes Erase unit Figure 7 1 Flash Memory Block Configuration 7 2 Register Descriptions The flash memory has the following registers For details on register addresse...

Page 99: ...ncelled Set this bit to 1 before setting the E bit to 1 in FLMCR1 4 PSU 0 R W Program Setup When this bit is set to 1 the flash memory changes to the program setup state When it is cleared to 0 the program setup state is cancelled Set this bit to 1 before setting the P bit in FLMCR1 3 EV 0 R W Erase Verify When this bit is set to 1 the flash memory changes to erase verify mode When it is cleared t...

Page 100: ...ed 7 2 3 Erase Block Register 1 EBR1 EBR1 specifies the flash memory erase area block EBR1 is initialized to H 00 when the SWE bit in FLMCR1 is 0 Do not set more than one bit at a time as this will cause all the bits in EBR1 to be automatically cleared to 0 Bit Bit Name Initial Value R W Description 7 6 5 0 0 0 Reserved These bits are always read as 0 and cannot be modified 4 EB4 0 R W When this b...

Page 101: ...es of HD64F3672 changes to a mode depending on the TEST pin settings NMI pin settings and input level of each port as shown in table 7 1 The input level of each pin must be defined four states before the reset ends When changing to boot mode the boot program built into this LSI is initiated The boot program transfers the programming control program from the externally connected host to on chip RAM...

Page 102: ...ode again by a reset Depending on the host s transfer bit rate and system clock frequency of this LSI there will be a discrepancy between the bit rates of the host and the chip To operate the SCI properly set the host s transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7 3 5 In boot mode a part of the on chip RAM area is used by the boot program The area H ...

Page 103: ...yte following high order byte Transmits 1 byte of programming control program Transfer of programming control program Execution of Programming control program Transfer of programming control program repeated for N times Flash memory erase Echobacks the 2 byte received data to host Branches to programming control program transferred to on chip RAM and starts execution Echobacks received data to hos...

Page 104: ...h memory itself cannot be read during programming erasing transfer the user program erase control program to on chip RAM as in boot mode Figure 7 2 shows a sample procedure for programming erasing in user program mode Prepare a user program erase control program in accordance with the description in section 7 4 Flash Memory Programming Erasing Yes No Program erase Transfer user program erase contr...

Page 105: ...y been performed 2 Programming should be carried out 128 bytes at a time A 128 byte data transfer must be performed even if writing fewer than 128 bytes In this case H FF data must be written to the extra addresses 3 Prepare the following data storage areas in RAM A 128 byte programming data area a 128 byte reprogramming data area and a 128 byte additional programming data area Perform reprogrammi...

Page 106: ...tation Additional programming data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 m 1 m 0 Increment address Programming failure No Clear SWE bit in FLMCR1 Wait 100 µs No Yes n 6 No Yes n 6 Wait 100 µs n 1000 n n 1 Write 128 byte data in RAM reprogram data area consecutively to flash memory Store 128 byte program data in program data area and reprogram data area Apply Write Pulse Sub Ro...

Page 107: ...a Additional Program Data Comments 0 0 0 Additional program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Table 7 6 Programming Time n Number of Writes Programming Time In Additional Programming Comments 1 to 6 30 10 7 to 1 000 200 Note Time shown in µs ...

Page 108: ...longwords from the address to which a dummy write was performed 6 If the read data is not erased erased successfully set erase mode again and repeat the erase erase verify sequence as before The maximum number of repetitions of the erase erase verify sequence is 100 7 4 3 Interrupt Handling when Programming Erasing Flash Memory All interrupts including the NMI interrupt are disabled while flash me...

Page 109: ...data Increment address Verify data all 1s Last address of block All erase block erased Set block start address as verify address H FF dummy write to verify address Wait 20 µs Wait 2 µs EV bit 1 Wait 100 µs End of erasing SWE bit 0 Wait 4 µs EV bit 0 n 100 Wait 100 µs Erase failure SWE bit 0 Wait 4µs EV bit 0 n n 1 Yes No Yes Yes Yes Yes No No No Figure 7 4 Erase Erase Verify Flowchart ...

Page 110: ...lock register 1 EBR1 erase protection can be set for individual blocks When EBR1 is set to H 00 erase protection is set for all blocks 7 5 3 Error Protection In error protection an error is detected when CPU runaway occurs during flash memory programming erasing or operation is not performed in accordance with the program erase algorithm and the program erase operation is aborted Aborting the prog...

Page 111: ...03 01 page 87 of 280 Section 8 RAM This LSI has 2 kbyte of on chip high speed static RAM The RAM is connected to the CPU by a 16 bit data bus enabling two state access by the CPU to both byte data and word data ...

Page 112: ...Rev 1 0 03 01 page 88 of 280 ...

Page 113: ...the port control register for controlling inputs outputs and the port data register for storing output data and can select inputs outputs in bit units For functions in each port see appendix C 1 I O Port Block Diagrams For the execution of bit manipulation instructions to the port control register and port data register see 2 8 3 Bit Manipulation Instruction 9 1 Port 1 Port 1 is a general I O port...

Page 114: ... These bits are always read as 0 and cannot be modified 4 IRQ0 0 R W P14 IRQ0 Pin Function Switch This bit selects whether pin P14 IRQ0 is used as P14 or as IRQ0 0 P14 I O port 1 IRQ0 input pin 3 1 Reserved This bit is always read as 1 and cannnot be modified 2 0 Reserved This bit must always be cleared to 0 setting to 1 is disabled 1 TXD 0 R W P22 TXD Pin Function Switch This bit selects whether ...

Page 115: ...output port while clearing the bit to 0 makes the pin an input port Bit 3 is a reserved bit 9 1 3 Port Data Register 1 PDR1 PDR1 is a general I O port data register of port 1 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P12 P11 P10 0 0 0 0 1 0 0 0 R W R W R W R W R W R W R W PDR1 stores output data for port 1 pins If PDR1 is read while PCR1 bits are set to 1 the value...

Page 116: ... P12 to P10 pins enter the on state when these bits are set to 1 while they enter the off state when these bits are cleared to 0 Bit 3 is a reserved bit This bit is always read as 1 and cannot be modified 9 1 5 Pin Functions The correspondence between the register specification and the port functions is shown below P17 IRQ3 TRGV pin Register PMR1 PCR1 Bit Name IRQ3 PCR17 Pin Function Setting value...

Page 117: ...ction Setting value 0 0 P14 input pin 0 1 P14 output pin 1 X IRQ0 input pin Legend X Don t care P12 pin Register PCR1 Bit Name PCR12 Pin Function 0 P12 input pin Setting value 1 P12 output pin P11 pin Register PCR1 Bit Name PCR11 Pin Function 0 P11 input pin Setting value 1 P11 output pin P10 pin Register PCR1 Bit Name PCR10 Pin Function Setting value 0 P10 input pin 1 P10 output pin ...

Page 118: ...r addresses and register states during each process refer to appendix B Internal I O Registers Port control register 2 PCR2 Port data register 2 PDR2 9 2 1 Port Control Register 2 PCR2 PCR2 selects inputs outputs in bit units for pins to be used as general I O ports of port 2 Bit Bit Name Initial Value R W Description 7 6 5 4 3 Reserved 2 1 0 PCR22 PCR21 PCR20 0 0 0 W W W When each of the port 2 p...

Page 119: ...he value stored in PDR2 is read If PDR2 is read while PCR2 bits are cleared to 0 the pin states are read regardless of the value stored in PDR2 9 2 3 Pin Functions The correspondence between the register specification and the port functions is shown below P22 TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Pin Function Setting Value 0 0 P22 input pin 0 1 P22 output pin 1 X TXD output pin Legend X Do...

Page 120: ...eneral I O port also functioning as an A D trigger input pin and wakeup interrupt input pin Each pin of the port 5 is shown in figure 9 3 P57 P56 P55 P54 P53 P52 P51 P50 Port 5 Figure 9 3 Port 5 Pin Configuration Port 5 has the following registers For details on register addresses and register states during each process refer to appendix B Internal I O Register Port mode register 5 PMR5 Port contr...

Page 121: ...ut pin 4 WKP4 0 R W P54 WKP4 Pin Function Switch Selects whether pin P54 WKP4 is used as P54 or as WKP4 0 P54 I O port 1 WKP4 input pin 3 WKP3 0 R W P53 WKP3 Pin Function Switch Selects whether pin P53 WKP3 is used as P53 or as WKP3 0 P53 I O port 1 WKP3 input pin 2 WKP2 0 R W P52 WKP2 Pin Function Switch Selects whether pin P52 WKP2 is used as P52 or as WKP2 0 P52 I O port 1 WKP2 input pin 1 WKP1...

Page 122: ...setting a PCR5 bit to 1 makes the corresponding pin an output port while clearing the bit to 0 makes the pin an input port 9 3 3 Port Data Register 5 PDR5 PDR5 is a general I O port data register of port 5 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Stores output data for port 5 pins If PDR5 is read whil...

Page 123: ...ared are valid The pull up MOS of the corresponding pins enter the on state when these bits are set to 1 while they enter the off state when these bits are cleared to 0 9 3 5 Pin Functions The correspondence between the register specification and the port functions is shown below P57 pin Register PMR5 PCR5 Bit Name POF7 PCR57 Pin Function Setting Value X 0 P57 input pin 0 1 CMOS output 1 1 NMOS op...

Page 124: ...it Name WKP4 PCR54 Pin Function Setting Value 0 0 P54 input pin 0 1 P54 output pin 1 X WKP4 input pin Legend X Don t care P53 WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function Setting Value 0 0 P53 input pin 0 1 P53 output pin 1 X WKP3 input pin Legend X Don t care P52 WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting Value 0 0 P52 input pin 0 1 P52 output pin 1 X WKP...

Page 125: ...ioning as a Timer V I O pin Each pin of the port 7 is shown in figure 9 4 The register setting of TCSRV in timer V has priority for functions of pin P76 TMOV The pins P75 TMCIV and P74 TMRIV are also functioning as timer V input ports that are connected to the timer V regardless of the register setting of port 7 P76 TMOV P75 TMCIV P74 TMRIV Port 7 Figure 9 4 Port 7 Pin Configuration Port 7 has the...

Page 126: ...s priority for deciding input output direction of the P76 TMOV pin 3 2 1 0 Reserved 9 4 2 Port Data Register 7 PDR7 PDR7 is a general I O port data register of port 7 Bit Bit Name Initial Value R W Description 7 1 Reserved This bit is always read as 1 and cannot be modified 6 5 4 P76 P75 P74 0 0 0 R W R W R W PDR7 stores output data for port 7 pins PDR7 is read while PCR7 bits are set to 1 the val...

Page 127: ...S0 PCR76 Pin Function Setting Value 0000 0 P76 input pin 1 P76 output pin Other than the above values X TMOV output pin Legend X Don t care P75 TMCIV pin Register PCR7 Bit Name PCR75 Pin Function Setting Value 0 P75 input TMCIV input pin 1 P75 output TMCIV input pin P74 TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input TMRIV input pin 1 P74 output TMRIV input pin ...

Page 128: ...as the following registers For details on register addresses and register states during each process refer to appendix B Internal I O Registers Port control register 8 PCR8 Port data register 8 PDR8 9 5 1 Port Control Register 8 PCR8 PCR8 selects inputs outputs in bit units for pins to be used as general I O ports of port 8 Bit Bit Name Initial Value R W Description 7 6 5 0 0 0 Reserved These bits...

Page 129: ...in PDR8 is read If PDR8 is read while PCR8 bits are cleared to 0 the pin states are read regardless of the value stored in PDR8 9 5 3 Pin Functions The correspondence between the register specification and the port functions is shown below P84 FTIOD pin Register TIOR1 PCR8 Bit Name IOD2 IOD1 IOD0 PCR84 Pin Function Setting Value 0 0 0 0 P84 input FTIOD input pin 0 0 0 1 P84 output FTIOD input pin ...

Page 130: ... Bit Name IOB2 IOB1 IOB0 PCR82 Pin Function Setting Value 0 0 0 0 P82 input FTIOB input pin 0 0 0 1 P82 output FTIOB input pin 0 0 1 X FTIOB output pin 0 1 X X FTIOB output pin 1 X X 0 P82 input FTIOB input pin 1 X X 1 P82 output FTIOB input pin Legend X Don t care P81 FTIOA pin Register TIOR0 PCR8 Bit Name IOA2 IOA1 IOA0 PCR81 Pin Function Setting Value 0 0 0 0 P81 input FTIOA input pin 0 0 0 1 P...

Page 131: ...B is an input port also functioning as an A D converter analog input pin Each pin of the port B is shown in figure 9 6 PB3 AN3 PB2 AN2 PB1 AN1 PB0 AN0 Port B Figure 9 6 Port B Pin Configuration Port B has the following registers For details on register addresses and register states during each process refer to appendix B Internal I O Registers Port data register B PDRB ...

Page 132: ...only port data register of port B Bit Bit Name Initial Value R W Description 7 6 5 4 Reserved 3 2 1 0 PB3 PB2 PB1 PB0 R R R R The input value of each pin is read by reading this register However if a port B pin is designated as an analog input channel by ADCSR in A D converter 0 is read ...

Page 133: ...V 10 1 Features Choice of seven clock signals are available Choice of six internal clock sources ø 128 ø 64 ø 32 ø 16 ø 8 ø 4 or an external clock can be used as an external event counter Counter can be cleared by compare match A or B or by an external reset signal If the count stop function is selected the counter can be halted when cleared Timer output is controlled by two independent compare ma...

Page 134: ...ter V TCRV0 Timer control register V0 TCRV1 Timer control register V1 PSS Prescaler S CMIA Compare match interrupt A CMIB Compare match interrupt B OVI Overflow interupt Figure 10 1 Block Diagram of Timer V 10 2 Input Output Pins Table 10 1 shows the timer V pin configuration Table 10 1 Pin Configuration Name Abbrev I O Function Timer V output TMOV Output Timer V waveform output Timer V clock inpu...

Page 135: ...CNTV can be cleared by an external reset input signal or by compare match A or B The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0 When TCNTV overflows OVF is set to 1 in Timer Control Status Register V TCSRV TCNTV is initialized to H 00 10 3 2 Time Constant Registers A and B TCORA TCORB TCORA and TCORB have the same function TCORA and TCORB are 8 bit read write registers TCORA and ...

Page 136: ...uest from the CMFA bit in TCSRV is enabled 5 OVIE 0 R W Timer Overflow Interrupt Enable When this bit is set to 1 interrupt request from the OVF bit in TCSRV is enabled 4 3 CCLR1 CCLR0 0 0 R W R W Counter Clear 1 and 0 These bits specify the clearing conditions of TCNTV 00 Clearing is disabled 01 Cleared by compare match A 10 Cleared by compare match B 11 Cleared on the rising edge of the TMRIV pi...

Page 137: ... counts on φ 4 falling edge 1 Internal clock counts on φ 8 falling edge 1 0 0 Internal clock counts on φ 16 falling edge 1 Internal clock counts on φ 32 falling edge 1 0 Internal clock counts on φ 64 falling edge 1 Internal clock counts on φ 128 falling edge 1 0 0 Clock input disabled 1 External clock counts on rising edge 1 0 External clock counts on falling edge 1 External clock counts on rising...

Page 138: ...g condition After reading CMFA 1 cleared by writing 0 to CMFA 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNTV overflows from H FF to H 00 Clearing condition After reading OVF 1 cleared by writing 0 to OVF 4 1 Reserved This bit is always read as 1 and cannot be modified 3 2 OS3 OS2 0 0 R W R W Output Select 3 and 2 These bits select an output method for the TOMV pin by the compare matc...

Page 139: ... is selected 10 Falling edge is selected 11 Rising and falling edges are both selected 2 TRGE 0 R W TRGV Input Enable This bit disables starting counting up TCNTV by the input of the TRGV pin and halting counting up TCNTV when TCNTV is cleared by a compare match 1 1 Reserved This bit is always read as 1 and cannot be modified 0 ICKS0 0 R W Internal Clock Select 0 This bit selects clock signals to ...

Page 140: ...ted the TMOV responds with the output value selected by bits OS3 to OS0 in TCSRV Figure 10 6 shows the timing when the output is toggled by compare match A 5 When CCLR1 or CCLR0 in TCRV0 is 01 or 10 TCNTV can be cleared by the corresponding compare match Figure 10 7 shows the timing 6 When CCLR1 or CCLR0 in TCRV0 is 11 TCNTV can be cleared by the rising edge of the input of TMRIV pin A TMRIV input...

Page 141: ...l clock input pin TCNTV input clock TCNTV Figure 10 3 Increment Timing with External Clock H FF H 00 ø TCNTV Overflow signal OVF Figure 10 4 OVF Set Timing N N N 1 ø TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 10 5 CMFA and CMFB Set Timing ...

Page 142: ...tch A signal Timer V output pin Figure 10 6 TMOV Output Timing N H 00 ø Compare match A signal TCNTV Figure 10 7 Clear Timing by Compare Match N 1 N H 00 ø Compare match A signal Timer V output pin TCNTV Figure 10 8 Clear Timing by TMRIV Input ...

Page 143: ...tch with TCORA 2 Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB 3 Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source 4 With these settings a waveform is output without further software intervention with a period determined by TCORA and a pulse width determined by TCORB Counter clear...

Page 144: ... and to 0 at compare match with TCORB 3 Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV input 4 Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source 5 After these settings a pulse waveform will be output without further software intervention with a delay determined by TCORA from the TRGV input and a pulse width determined by...

Page 145: ...ng 3 If compare matches A and B occur simultaneously any conflict between the output selections for compare match A and compare match B is resolved by the following priority toggle output output 1 output 0 4 Depending on the timing TCNTV may be incremented by a switch between different internal clock sources When TCNTV is internally clocked an increment pulse is generated from the falling edge of ...

Page 146: ... TCORA write data Inhibited T1 T2 T3 TCORA write cycle by CPU Compare match signal Figure 10 12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N 1 N 2 Write to CKS1 and CKS0 Figure 10 13 Internal Clock Switching and TCNTV Operation ...

Page 147: ...ters Independently assignable output compare or input capture functions Usable as two pairs of registers one register of each pair operates as a buffer for the output compare or input capture register Four selectable operating modes Waveform output by compare match Selection of 0 output 1 output or toggle output Input capture function Rising edge falling edge or both edges Counter clearing functio...

Page 148: ... for GRA in buffer mode GRD buffer register for GRB in buffer mode Counter clearing function GRA compare match GRA compare match Initial output value setting function Yes Yes Yes Yes Buffer function Yes Yes Compare 0 Yes Yes Yes Yes match output 1 Yes Yes Yes Yes Toggle Yes Yes Yes Yes Input capture function Yes Yes Yes Yes PWM mode Yes Yes Yes Interrupt sources Overflow Compare match input captur...

Page 149: ...16 bits IRRIW Timer W interrupt request GRA GRB GRC GRD TMRW TCRW TIERW TSRW TIOR ø ø 2 ø 4 ø 8 Figure 11 1 Timer W Block Diagram 11 2 Input Output Pins Table 11 2 summarizes the timer W pins Table 11 2 Timer W Pins Name Abbreviation Input Output Function External clock input FTCI Input External clock input pin Input capture output compare A FTIOA Input output Output pin for GRA output compare or ...

Page 150: ...egister W TMRW Timer control register W TCRW Timer interrupt enable register W TIERW Timer status register W TSRW Timer I O control register 0 TIOR0 Timer I O control register 1 TIOR1 Timer counter TCNT General register A GRA General register B GRB General register C GRC General register D GRD 11 3 1 Timer Mode Register W TMRW The timer mode register W TMRW selects the general register functions a...

Page 151: ...r for GRB 4 BUFEA 0 R W Buffer Operation A Selects the GRC function 0 GRC operates as an input capture output compare register 1 GRC operates as the buffer register for GRA 3 1 Reserved This bit is always read as 1 and cannot be modified 2 PWMD 0 R W PWM Mode D Selects the output mode of the FTIOD pin 0 FTIOD operates normally output compare output 1 PWM output 1 PWMC 0 R W PWM Mode C Selects the ...

Page 152: ...hen the internal clock source φ is selected subclock sources are counted in subactive and subsleep modes 3 TOD 0 R W Timer Output Level Setting D Sets the output value of the FTIOD pin until the first compare match D is generated 0 Initial output value is 0 1 Initial output value is 1 2 TOC 0 R W Timer Output Level Setting C Sets the output value of the FTIOC pin until the first compare match C is...

Page 153: ...upt Enable C When this bit is set to 1 IMIC interrupt requested by IMFC flag in TSRW is enabled 1 IMIEB 0 R W Input Capture Compare Match Interrupt Enable B When this bit is set to 1 IMIB interrupt requested by IMFB flag in TSRW is enabled 0 IMIEA 0 R W Input Capture Compare Match Interrupt Enable A When this bit is set to 1 IMIA interrupt requested by IMFA flag in TSRW is enabled 11 3 4 Timer Sta...

Page 154: ... by an input capture signal when GRC functions as an input capture register Clearing condition Read IMFC when IMFC 1 then write 0 in IMFC 1 IMFB 0 R W Input Capture Compare Match Flag B Setting conditions TCNT GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register Clearing condition Read I...

Page 155: ...at GRB compare match When IOB2 1 00 Input capture at rising edge at the FTIOB pin 01 Input capture at falling edge at the FTIOB pin 1X Input capture at rising edge and falling edge at the FTIOB pin 3 1 Reserved This bit is always read as 1 and cannot be modified 2 IOA2 0 R W I O Control A2 Selects the GRA function 0 GRA functions as an output compare register 1 GRA functions as an input capture re...

Page 156: ...pare match When IOD2 1 00 Input capture at rising edge at the FTIOD pin 01 Input capture at falling edge at the FTIOD pin 1X Input capture at rising edge and falling edge at the FTIOD pin 3 1 Reserved This bit is always read as 1 and cannot be modified 2 IOC2 0 R W I O Control C2 Selects the GRC function 0 GRC functions as an output compare register 1 GRC functions as an input capture register 1 0...

Page 157: ...upt request is generated at this time when IMIEA IMIEB IMIEC or IMIED is set to 1 Compare match output can be selected in TIOR When a general register is used as an input capture register an external input capture signal is detected and the current TCNT value is stored in the general register The corresponding flag IMFA IMFB IMFC or IMFD in TSRW is set to 1 If the corresponding interrupt enable bi...

Page 158: ...E in TIERW is set to 1 an interrupt request is generated Figure 11 2 shows free running counting TCNT value H FFFF H 0000 CST bit OVF Time Flag cleared by software Figure 11 2 Free Running Counter Operation Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1 When the count matches GRA TCNT is cleared to H 0000 the IMFA flag in...

Page 159: ...of 0 and 1 output when TCNT operates as a free running counter 1 output is selected for compare match A and 0 output is selected for compare match B When signal is already at the selected output level the signal level does not change at compare match TCNT value H FFFF H 0000 FTIOA FTIOB Time GRA GRB No change No change No change No change Figure 11 4 0 and 1 Output Example TOA 0 TOB 1 Figure 11 5 ...

Page 160: ...gle output Toggle output Counter cleared by compare match with GRA Figure 11 6 Toggle Output Example TOA 0 TOB 1 The TCNT value can be captured into a general register GRA GRB GRC or GRD when a signal level changes at an input capture pin FTIOA FTIOB FTIOC or FTIOD Capture can take place on the rising edge falling edge or both edges By using the input capture function the pulse width and periods c...

Page 161: ...s an input capture register and GRC is set as the buffer register for GRA TCNT operates as a free running counter and FTIOA captures both rising and falling edge of the input signal Due to the buffer operation the GRA value is transferred to GRC by input capture A and the TCNT value is stored in GRA TCNT value H DA91 H 0245 H 0000 GRC Time H 0245 FTIOA GRA H 5480 H 0245 H FFFF H 5480 H 5480 H DA91...

Page 162: ...ut level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode If the same value is set in the cycle register and the duty register the output does not change when a compare match occurs Figure 11 9 shows an example of a procedure for setting up PWM mode Figure 11 9 shows an example of operation in PWM mode The output signals go to 1 and TCNT is cleared at compare match A and ...

Page 163: ...TIOB outputs 1 at compare match B and 0 at compare match A Due to the buffer operation the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs This procedure is repeated every time compare match B occurs TCNT value GRA H 0000 GRD Time GRB H 0200 H 0520 FTIOB H 0200 H 0450 H 0520 H 0450 GRB H 0450 H 0520 H 0200 Figure 11 11 Buffer Op...

Page 164: ...t does not change when cycle register and duty register compare matches occur simultaneously TCNT value GRA H 0000 FTIOB Time GRB Duty 100 Write to GRB Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously Duty 0 Write to GRB Figure 11 12 PWM Mode Example TOB 0 TOC 0 TOD 0 initial output values are set to 0 ...

Page 165: ...ge when cycle register and duty register compare matches occur simultaneously TCNT value GRA H 0000 FTIOB Time GRB Duty 0 Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously Duty 100 Write to GRB Write to GRB Write to GRB Figure 11 13 PWM Mode Example TOB 1 TOC 1 and TOD 1 initial output values are set to 1 ...

Page 166: ...ure 11 14 Count Timing for Internal Clock Source TCNT TCNT input clock External clock φ N N 1 N 2 Rising edge Rising edge Figure 11 15 Count Timing for External Clock Source 11 5 2 Output Compare Timing The compare match signal is generated in the last state in which TCNT and the general register match when TCNT changes from the matching value to the next value When the compare match signal is gen...

Page 167: ...put capture on the rising edge falling edge or both edges can be selected through settings in TIOR0 and TIOR1 Figure 11 17 shows the timing when the falling edge is selected The pulse width of the input capture signal must be at least two system clock φ cycles shorter pulses will not be detected correctly TCNT Input capture input ø N 1 N N 1 N 2 N GRA to GRD Input capture signal Figure 11 17 Input...

Page 168: ... the GRA value is N the counter counts from 0 to N and its cycle is N 1 TCNT Compare match signal φ GRA N N H 0000 Figure 11 18 Timing of Counter Clearing by Compare Match 11 5 5 Buffer Operation Timing Figures 11 19 and 12 20 show the buffer operation timing GRC GRD Compare match signal TCNT φ GRA GRB N N 1 M M Figure 11 19 Buffer Operation Timing Compare Match ...

Page 169: ...hen TCNT matches the general register The compare match signal is generated in the last state in which the values match when TCNT is updated from the matching count to the next count Therefore when TCNT matches a general register the compare match signal is generated only after the next TCNT clock pulse is input Figure 11 21 shows the timing of the IMFA to IMFD flag setting at compare match GRA to...

Page 170: ...to IMFD flag setting at input capture GRA to GRD TCNT Input capture signal φ N N IMFA to IMFD IRRTW Figure 11 22 Timing of IMFA to IMFD Flag Setting at Input Capture Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1 then writes 0 in the status flag the status flag is cleared Figure 11 23 shows the status flag clearing timing IMFA to IMFD Write signal Address φ TS...

Page 171: ...with the TCNT counting up writing takes precedence 3 Depending on the timing TCNT may be incremented by a switch between different internal clock sources When TCNT is internally clocked an increment pulse is generated from the rising edge of an internal clock signal that is divided system clock φ Therefore as shown in figure 11 25 the switch is from a low clock signal to a high clock signal the sw...

Page 172: ...f 280 TCNT Previous clock N N 1 N 2 N 3 New clock Count clock The change in signal level at clock switching is assumed to be a rising edge and TCNT increments the count Figure 11 25 Internal Clock Switching and TCNT Operation ...

Page 173: ...lock Diagram of WDT 12 1 Features Selectable from nine counter input clocks Eight clock sources φ 64 φ 128 φ 256 φ 512 φ 1024 φ 2048 φ 4096 φ 8192 or the internal oscillator can be selected as the timer counter clock When the internal oscillator is selected it can operate as the watchdog timer in any operating mode except in standby mode Reset signal generated on counter overflow An overflow perio...

Page 174: ...read as 1 4 TCSRWE 0 R W Timer Control Status Register W Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1 When writing data to this bit the value for bit 5 must be 0 3 B2WI 1 R Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0 This bit is always read as 1 2 WDON 0 R W Watchdog Timer On TCWD starts counting u...

Page 175: ...ster WD TMWD TMWD is an 8 bit readable writable register that selects the input clock Bit Bit Name Initial Value R W Description 7 6 5 4 1 1 1 1 Reserved These bits are always read as 1 3 2 1 0 CKS3 CKS2 CKS1 CKS0 1 1 1 1 R W R W R W R W Clock Select 3 to 0 Select the clock to be input to TCWD 1000 Internal clock counts on φ 64 1001 Internal clock counts on φ 128 1010 Internal clock counts on φ 25...

Page 176: ...he internal reset signal is output for a period of 512 φosc clock cycles TCWD is a writable counter and when a value is set in TCWD the count up starts from that value An overflow period in the range of 1 to 256 input clock cycles can therefore be set according to the TCWD set value Figure 12 2 shows an example of watchdog timer operation Example With 30ms overflow period when φ 4 MHz 4 106 30 10 ...

Page 177: ...eceiver are mutually independent enabling transmission and reception to be executed simultaneously Double buffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data On chip baud rate generator allows any bit rate to be selected External clock or on chip baud rate generator can be selected as a transfer clock source except for...

Page 178: ... SMR SCR3 SSR BRR BRC Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Interrupt request TEI TXI RXI ERI Internal clock ø 64 ø 16 ø 4 ø External clock BRC Baud rate generator Figure 13 1 Block Diagram of SCI3 ...

Page 179: ...ransmit data output TXD Output SCI3 transmit data output 13 3 Register Descriptions The SCI3 has the following registers for each channel For details on register addresses and register states during each process refer to appendix B Internal I O Register Receive Shift Register RSR Receive Data Register RDR Transmit Shift Register TSR Transmit Data Register TDR Serial Mode Register SMR Serial Contro...

Page 180: ... written to by the CPU RDR is initialized to H 00 13 3 3 Transmit Shift Register TSR TSR is a shift register that transmits serial data To perform serial data transmission the SCI first transfers transmit data from TDR to TSR automatically then sends the data that starts from the LSB to the TXD pin TSR cannot be directly accessed by the CPU 13 3 4 Transmit Data Register TDR TDR is an 8 bit registe...

Page 181: ...e parity bit is added to transmit data before transmission and the parity bit is checked in reception 4 PM 0 R W Parity Mode enabled only when the PE bit is 1 in asynchronous mode 0 Selects even parity 1 Selects odd parity 3 STOP 0 R W Stop Bit Length enabled only in asynchronous mode Selects the stop bit length in transmission 0 1 stop bit 1 2 stop bits For reception only the first stop bit is ch...

Page 182: ...er BRR 13 3 6 Serial Control Register 3 SCR3 SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests and is also used to selection of the transfer clock source For details on interrupt requests refer to section 13 7 Interrupts Bit Bit Name Initial Value R W Description 7 TIE 0 R W Transmit Interrupt Enable When this bit is set to 1 the TXI interrupt request is e...

Page 183: ...etails refer to section 13 6 Multiprocessor Communication Function 2 TEIE 0 R W Transmit End Interrupt Enable This bit is set to 1 TEI interrupt request is enabled 1 0 CKE1 CKE0 0 0 R W R W Clock Enable 0 and 1 Selects the clock source Asynchronous mode 00 Internal baud rate generator 01 Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin 10 Externa...

Page 184: ...hen data is transferred from TDR to TSR and data can be written to TDR Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the transmit data is written to TDR 6 RDRF 0 R W Receive Data Register Full Indicates that the received data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to RDR Clearing conditions When 0 is...

Page 185: ...eading PER 1 2 TEND 0 R Transmit End Setting conditions When the TE bit in SCR3 is 0 When TDRE 1 at transmission of the last bit of a 1 byte serial transmit character Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the transmit data is written to TDR 1 MPBR 0 R Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data When the RE bit in SCR...

Page 186: ...3 2 and 13 3 are values in active high speed mode Table 13 4 shows the relationship between the N setting in BRR and the N setting in bits CKS1 and CKS0 of SMR in clocked synchronous mode The values shown in table 13 4 are values in active high speed mode The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas Asynchronous mode N φ 106...

Page 187: ... 00 0 9 2 34 19200 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 Legend A setting is available but error occurs Operating Frequency ø MHz 3 6864 4 4 9152 5 Bit Rate bits s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 1...

Page 188: ...34 0 19 0 00 0 23 0 00 19200 0 7 1 73 0 9 2 34 0 9 0 00 0 11 0 00 31250 0 4 0 00 0 5 0 00 0 5 2 40 0 6 5 33 38400 0 3 1 73 0 4 2 34 0 4 0 00 0 5 0 00 Operating Frequency ø MHz 8 9 8304 10 12 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 141 0 03 2 174 0 26 2 177 0 25 2 212 0 03 150 2 103 0 16 2 127 0 00 2 129 0 16 2 155 0 16 300 1 207 0 16 1 255 0 00 2 64 0 16 2 77 0 16 600 1 103 0 ...

Page 189: ...6 4800 0 79 0 00 0 90 0 16 0 95 0 00 0 103 0 16 9600 0 39 0 00 0 45 0 93 0 47 0 00 0 51 0 16 19200 0 19 0 00 0 22 0 93 0 23 0 00 0 25 0 16 31250 0 11 2 40 0 13 0 00 0 14 1 70 0 15 0 00 38400 0 9 0 00 0 11 0 00 0 12 0 16 Legend A setting is available but error occurs Table 13 3 Maximum Bit Rate for Each Frequency Asynchronous Mode ø MHz Maximum Bit Rate bit s n N ø MHz Maximum Bit Rate bit s n N 2 ...

Page 190: ...4 2 249 3 124 1k 1 124 1 249 2 124 2 249 2 5k 0 199 1 99 1 199 1 249 2 99 5k 0 99 0 199 1 99 1 124 1 199 10k 0 49 0 99 0 199 0 249 1 99 25k 0 19 0 39 0 79 0 99 0 159 50k 0 9 0 19 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 1 0 3 0 7 0 9 0 15 500k 0 0 0 1 0 3 0 4 0 7 1M 0 0 0 1 0 3 2M 0 0 0 1 2 5M 0 0 4M 0 0 Legend Blank No setting is available A setting is available but error occurs Continuo...

Page 191: ...mitter and receiver are independent units enabling full duplex Both the transmitter and the receiver also have a double buffered structure so data can be read or written during transmission or reception enabling continuous data transfer LSB Start bit MSB Idle state mark state Stop bit 0 Transmit receive data D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1...

Page 192: ... the clock frequency should be 16 times the bit rate used When the SCI3 is operated on an internal clock the clock can be output from the SCK3 pin The frequency of the clock output in this case is equal to the bit rate and the phase is such that the rising edge of the clock is in the middle of the transmit data as shown in figure 13 3 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Serial data Fig...

Page 193: ...SCR3 to 1 and set RIE TIE TEIE and MPIE bits For transmit TE 1 also set the TXD bit in PMR1 4 1 bit interval elapsed 1 Set the clock selection in SCR3 Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When the clock output is selected in asynchronous mode clock is output immediately after CKE1 and CKE0 settings are made When the clock output is selected at reception in asynchrono...

Page 194: ...he TDRE flag at the timing for sending the stop bit 4 If the TDRE flag is 0 the data is transferred from TDR to TSR the stop bit is sent and then serial transmission of the next frame is started 5 If the TDRE flag is 1 the TEND flag in SSR is set to 1 the stop bit is sent and then the mark state is entered in which 1 is output If the TEIE bit in SCR3 is set to 1 at this time a TEI interrupt reques...

Page 195: ...is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic 2 To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic 3 To output a break in serial transmission set PCR to 1 and PDR to 0 c...

Page 196: ...ted 4 If a framing error is detected when the stop bit is 0 the FER bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR3 is set to 1 at this time an ERI interrupt request is generated 5 If reception is completed successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR3 is set to 1 at this time an RXI interrupt request...

Page 197: ...0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error framing error 1 1 0 1 Lost Overrun error parity error 0 0 1 1 Transferred to RDR Framing error parity error 1 1 1 1 Lost Overrun error framing error parity error Note The RDRF flag retains the state it had before data reception ...

Page 198: ...n SSR to identify the error If a receive error occurs performs the appropriate error processing 2 SCI status check and receive data read Read SSR and check that RDRF 1 then read the receive data in RDR and clear the RDRF flag to 0 The RDRF flag is cleared automatically 3 To continue serial reception before the stop bit for the current frame is received read the RDRF flag read RDR and clear the RDR...

Page 199: ...ing Parity error processing Yes No Clear OER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing OER 1 FER 1 Break PER 1 Clear RE bit in SCR3 to 0 4 Figure 13 8 Sample Serial Reception Data Flowchart 2 ...

Page 200: ...n clock Both the transmitter and the receiver also have a double buffered structure so data can be read or written during transmission or reception enabling continuous data transfer Don t care Don t care One unit of transfer data character or frame 8 bit Bit 0 Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note High except in continuous transfer Figure 13 9 Dat...

Page 201: ...E flag at the timing for sending the MSB bit 7 5 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the next frame is started 6 If the TDRE flag is set to 1 the TEND flag in SSR is set to 1 and the TDRE flag maintains the output state of the last bit If the TEIE bit in SCR3 is set to 1 at this time a TEI interrupt request is generated 7 The SCK3 pin is ...

Page 202: ... then write transmit data to TDR and clear the TDRE flag to 0 When data is written to TDR the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission 2 To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR When data is written to TDR the TDRE flag is automatically cleared to 0 Figure 13 1...

Page 203: ...o RDR and the RDRF flag remains to be set to 1 4 If reception is completed successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR3 is set to 1 at this time an RXI interrupt request is generated Reception cannot be resumed while a receive error flag is set to 1 Accordingly clear the OER FER PER and RDRF bits to 0 before resuming reception Figure 13...

Page 204: ...rred execute overrun error processing 2 Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR When data is read from RDR the RDRF flag is automatically cleared to 0 3 To continue serial reception before the MSB bit 7 of the current frame is received reading the RDRF flag reading RDR and clearing the RDRF flag to 0 should be finished When data is read from RDR the RDRF...

Page 205: ...mode to simultaneous transmit and receive mode after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1 clear TE to 0 Then simultaneously set TE and RE to 1 with a single instruction To switch from receive mode to simultaneous transmit and receive mode after checking that the SCI3 has finished reception clear RE to 0 Then after checking that the RDRF and rece...

Page 206: ...to 0 3 To continue serial transmission reception before the MSB bit 7 of the current frame is received finish reading the RDRF flag reading RDR Also before the MSB bit 7 of the current frame is transmitted read 1 from the TDRE flag to confirm that writing is possible Then write data to TDR When data is written to TDR the TDRE flag is automatically cleared to 0 When data is read from RDR the RDRF f...

Page 207: ...h which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receives the data sent next Stations whose IDs do not match continue to skip data until data with ...

Page 208: ... 03 ID 04 Serial transmission line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 13 15 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A ...

Page 209: ... 3 Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR3 to 0 TDRE 1 All data transmitted TEND 1 Break output Write transmit data to TDR 1 Read SSR and check that the TDRE flag is set to 1 set the MPBT bit in SSR to 0 or 1 then write transmit data to TDR When data is written to TDR the TDRE flag is automatically cleared to 0 2 To continue serial transmission be sure to read 1 from the TDRE flag to ...

Page 210: ...it in SCR3 is set to 1 data is skipped until data with a 1 multiprocessor bit is sent On receiving data with a 1 multiprocessor bit the receive data is transferred to RDR An RXI interrupt request is generated at this time All other SCI3 operations are the same as in asynchronous mode Figure 13 18 shows an example of SCI3 operation for multiprocessor format reception ...

Page 211: ...eck that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 When data is read from RDR the RDRF flag is automatically cleared to 0 4 SCI status check and data reception Read SSR and check that the RDRF flag is set to 1 then read the data in RDR 5 If a receive...

Page 212: ...8 of 280 End Error processing Yes No Clear OER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing OER 1 FER 1 Break 5 A Figure 13 17 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 213: ...again 1 frame Start bit Start bit Receive data ID2 Receive data Data2 MPB MPB Stop bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 1 1 1 1 0 a When data does not match this receiver s ID b When data matches this receiver s ID D0 D1 D7 ID2 Data2 ID1 0 Serial data MPIE RDRF LSI operation RXI interrupt request MPIE cleared to 0 User processing RDRF flag cleared to 0 RXI interrupt request RDRF...

Page 214: ...DRE flag in SSR is 1 Thus when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR a TXI interrupt request is generated even if the transmit data is not ready The initial value of the TEND flag in SSR is 1 Thus when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR a TEI interrupt request is generated even if the transmit data has not been sent ...

Page 215: ...k during serial data transmission To maintain the communication line at mark state until TE is set to 1 set both PCR and PDR to 1 As TE is cleared to 0 at this point the TXD pin becomes an I O port and 1 is output from the TXD pin To send a break during serial transmission first set PCR to 1 and PDR to 0 and then clear TE to 0 When TE is cleared to 0 the transmitter is initialized regardless of th...

Page 216: ...nous mode is given by formula 1 below M 0 5 L 0 5 F 100 1 2N D 0 5 N Formula 1 Where N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F absolute value of clock rate deviation 0 and D clock duty 0 5 in formula 1 the reception margin can be given by the formula M 0 5 1 2 16 100 46 875 However this is only...

Page 217: ...t resolution Four input channels Conversion time at least 4 4 µs per channel at 16 MHz operation Two operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16 bit data register for each channel Sample and hold function Two methods conversion start Software External trigger signal Interrup...

Page 218: ...face Successive approximations register Analog multiplexer A D C S R A D C R A D D R D A D D R C A D D R B A D D R A AN0 AN1 AN2 AN3 Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D ø 4 ø 8 AVCC Figure 14 1 Block Diagram of A D Converter ...

Page 219: ...n Pin Name Symbol I O Function Analog power supply pin AVCC Input Analog block power supply and reference voltage Analog input pin 0 AN0 Input Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input analog input pins A D external trigger input pin ADTRG Input External trigger input pin for starting A D conversion ...

Page 220: ...hich store a conversion result for each channel are shown in table 14 2 The converted 10 bit data is stored in bits 6 to 15 The lower 6 bits are always read as 0 The data bus between the CPU and the A D converter is 8 bits wide The upper byte can be read directly from the CPU however the lower byte should be read via a temporary register The temporary register contents are transferred from the ADD...

Page 221: ...DST 0 R W A D Start Clearing this bit to 0 stops A D conversion and the A D converter enters the wait state Setting this bit to 1 starts A D conversion In single mode this bits is cleared to 0 automatically when conversion on the specified channel is complete In scan mode conversion continues sequentially on the specified channels until this bit is cleared to 0 by software a reset or a transition ...

Page 222: ...external trigger signal Bit Bit Name Initial Value R W Description 7 TRGE 0 R W Trigger Enable A D conversion is started at the falling edge and the rising edge of the external trigger signal ADTRG when this bit is set to 1 The selection between the falling edge and rising edge of the external trigger pin ADTRG comforms to the WPEG5 bit in the interrupt edge select register 2 IEGR2 6 5 4 3 2 1 1 1...

Page 223: ...it is set to 1 at this time an ADI interrupt request is generated 4 The ADST bit remains set to 1 during A D conversion When A D conversion ends the ADST bit is automatically cleared to 0 and the A D converter enters the wait state 14 4 2 Scan Mode In scan mode A D conversion is performed sequentially for the analog input on the specified channels four channels maximum as follows 1 When the ADST b...

Page 224: ...cludes tD and the input sampling time The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 14 3 In scan mode the values given in table 14 3 apply to the first conversion time In the second and subsequent conversions the conversion time is 128 states fixed when CKS 0 and 66 states fixed when CKS ...

Page 225: ...er Input Timing A D conversion can also be started by an external trigger input When the TRGE bit is set to 1 in ADCR external trigger input is enabled at the ADTRG pin A falling edge at the ADTRG input pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes are the same as when the bit ADST has been set to 1 by software Figure 14 3 shows the timi...

Page 226: ...from the minimum voltage value 0000000000 to 0000000001 see figure 14 5 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from 1111111110 to 1111111111 see figure 14 5 Absolute precision The deviation between the digital value and the analog input value Includes offset error full scale error quantization er...

Page 227: ...t be possible to guarantee A D conversion precision However for A D conversion in single mode with a large capacitance provided externally the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance is ignored However as a low pass filter effect is obtained in this case it may not be possible to follow an analog signal with a large different...

Page 228: ...ev 1 0 03 01 page 204 of 280 20 pF 10 k Cin 15 pF Sensor output impedance to 5 k This LSI Low pass filter C to 0 1 F Sensor input A D converter equivalent circuit Figure 14 6 Analog Input Circuit Example ...

Page 229: ...voltage without using the internal power supply step down circuit 15 1 When Using the Internal Power Supply Step Down Circuit Connect the external power supply to the VCC pin and connect a capacitance of approximately 0 1 µF between VCL and VCC as shown in figure 15 1 The internal step down circuit is made effective simply by adding this external circuit In the external circuit interface the exter...

Page 230: ...figure 15 2 The external power supply is then input directly to the internal power supply The permissible range for the power supply voltage is 3 0 V to 3 6 V Operation cannot be guaranteed if a voltage outside this range less than 3 0 V or more than 3 6 V is input VCL VSS Internal logic Step down circuit Internal power supply VCC VCC 3 0 to 3 6 V Figure 15 2 Power Supply Connection when Internal ...

Page 231: ...75 C Storage temperature Tstg 55 to 125 C Note Permanent damage may result if maximum ratings are exceeded Normal operation should be under the conditions specified in Electrical Characteristics Exceeding these values can result in incorrect operation and reduced reliability 16 2 Electrical Characteristics 16 2 1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Freque...

Page 232: ...1250 78 125 2000 3 0 4 0 5 5 VCC V ø kHz AVCC 3 3 V to 5 5 V Active mode Sleep mode When MA2 0 in SYSCR2 AVCC 3 3 V to 5 5 V Active mode Sleep mode When MA2 1 in SYSCR2 Analog Power Supply Voltage and A D Converter Accuracy Guarantee Range 10 0 2 0 16 0 3 3 4 0 5 5 AVCC V ø MHz VCC 3 0 V to 5 5 V Active mode Sleep mode ...

Page 233: ...CC 0 9 VCC 0 3 RXD P12 to P10 P17 to P14 P22 to P20 VCC 4 0 V to 5 5 V VCC 0 7 VCC 0 3 V P57 to P50 P76 to P74 P84 to P80 VCC 0 8 VCC 0 3 PB3 to PB0 VCC 4 0 V to 5 5 V VCC 0 7 AVCC 0 3 V VCC 0 8 AVCC 0 3 OSC1 VCC 4 0 V to 5 5 V VCC 0 5 VCC 0 3 V VCC 0 3 VCC 0 3 Input low voltage VIL RES WKP0 to WKP5 IRQ0 IRQ3 ADTRG TMRIV VCC 4 0 V to 5 5 V 0 3 VCC 0 2 V TMCIV FTCI FTIOA to FTIOD SCK3 TRGV 0 3 VCC ...

Page 234: ... P20 VCC 4 0 V to 5 5 V IOH 1 5 mA VCC 1 0 V P57 to P50 P76 to P74 P84 to P80 IOH 0 1 mA VCC 0 5 Output low voltage VOL P12 to P10 P17 to P14 P22 to P20 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 6 V P55 to P50 P76 to P74 IOL 0 4 mA 0 4 P84 to P80 VCC 4 0 V to 5 5 V IOL 20 0 mA 1 5 V VCC 4 0 V to 5 5 V IOL 10 0 mA 1 0 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 4 IOL 0 4 mA 0 4 ...

Page 235: ...V 1 0 µA PB3 to PB0 VIN 0 5 V to AVCC 0 5 V 1 0 µA Pull up MOS Ip P12 to P10 P17 to P14 VCC 5 0 V VIN 0 0 V 50 0 300 0 µA current P55 to P50 VCC 3 0 V VIN 0 0 V 60 0 Reference value Input capaci tance Cin All input pins except power supply pins f 1 MHz VIN 0 0 V Ta 25 C 15 0 pF Active mode current IOPE1 VCC Active mode 1 VCC 5 0 V fOSC 16 MHz 15 0 22 5 mA dissipation Active mode 1 VCC 3 0 V fOSC 1...

Page 236: ...0 V fOSC 10 MHz 6 5 Reference value ISLEEP2 VCC Sleep mode 2 VCC 5 0 V fOSC 16 MHz 1 7 2 5 mA Sleep mode 2 VCC 3 0 V fOSC 10 MHz 1 1 Reference value Standby mode current dissipation ISTBY VCC 32 kHz crystal oscillator not used 5 0 µA RAM data retaining voltage VRAM VCC 2 0 V Note Pin states during current dissipation measurement are given below excluding current in the pull up MOS transistors and ...

Page 237: ... to 5 5 V VSS 0 0 V Ta 20 C to 75 C unless otherwise indicated Applicable Values Item Symbol Pins Test Condition Min Typ Max Unit Allowable output low current per pin IOL Output pins except port 8 VCC 4 0 V to 5 5 V 2 0 mA Port 8 20 0 Port 8 10 0 Output pins except port 8 0 5 Allowable output low current total IOL Output pins except port 8 VCC 4 0 V to 5 5 V 40 0 mA Port 8 80 0 Output pins except ...

Page 238: ...quency 2 0 10 0 System clock ø tcyc 1 64 tOSC 2 cycle time 12 8 µs Instruction cycle time 2 tcyc Oscillation stabilization time crystal oscillator trc OSC1 OSC2 10 0 ms Oscillation stabilization time ceramic oscillator trc OSC1 OSC2 5 0 ms External clock tCPH OSC1 VCC 4 0 V to 5 5 V 25 0 ns Figure 16 1 high width 40 0 External clock tCPL OSC1 VCC 4 0 V to 5 5 V 25 0 ns low width 40 0 External cloc...

Page 239: ...n active mode and sleep mode operation 10 tcyc Input pin high width tIH IRQ0 IRQ3 WKP0 to WKP5 TMCIV TMRIV TRGV ADTRG FTCI FTIOA to FTIOD 2 tcyc Figure 16 3 Input pin low width tIL IRQ0 IRQ3 WKP0 to WKP5 TMCIV TMRIV TRGV ADTRG FTCI FTIOA to FTIOD 2 tcyc Notes 1 When an external clock is input the minimum system clock oscillator frequency is 1 0 MHz 2 Determined by MA2 to MA0 system control registe...

Page 240: ...yp Max Unit Figure Input clock Asynchro nous tScyc SCK3 4 tcyc Figure 16 4 cycle Synchro nous 6 Input clock pulse width tSCKW SCK3 0 4 0 6 tScyc Transmit data delay tTXD TXD VCC 4 0 V to 5 5 V 1 tcyc Figure 16 5 time clocked synchronous 1 Receive data setup tRXS RXD VCC 4 0 V to 5 5 V 62 5 ns time clocked synchronous 100 0 Receive data hold tRXH RXD VCC 4 0 V to 5 5 V 62 5 ns time clocked synchron...

Page 241: ...IOPE AVCC AVCC 5 0 V fOSC 16 MHz 2 0 mA AISTOP1 AVCC 50 µA 2 Reference value AISTOP2 AVCC 5 0 µA 3 Analog input capacitance CAIN AN3 to AN0 30 0 pF Allowable signal source impedance RAIN AN3 to AN0 5 0 kΩ Resolution data length 10 10 10 bit Conversion time single mode AVCC 3 3 V to 5 5 V 134 tcyc Nonlinearity error 7 5 LSB Offset error 7 5 LSB Full scale error 7 5 LSB Quantization error 0 5 LSB Ab...

Page 242: ... the current in active and sleep modes while the A D converter is idle 3 AISTOP2 is the current at reset in standby and in subsleep mode while the A D converter is idle 16 2 5 Watchdog Timer Table 16 6 Watchdog Timer Characteristics VCC 3 0 V to 5 5 V VSS 0 0 V Ta 20 C to 75 C unless otherwise specified Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure On chip osc...

Page 243: ...00 ms Reprogramming count NWEC 100 Times Programming Wait time after SWE bit setting 1 x 1 µs Wait time after PSU bit setting 1 y 50 µs Wait time after P bit setting z1 1 n 6 28 30 32 µs 1 4 z2 7 n 1000 198 200 202 µs z3 Additional programming 8 10 12 µs Wait time after P bit clear 1 α 5 µs Wait time after PSU bit clear 1 β 5 µs Wait time after PV bit setting 1 γ 4 µs Wait time after dummy write 1...

Page 244: ...er 1 FLMCR1 is set The program verify time is not included 3 The time required to erase one block Indicates the time for which the E bit in flash memory control register 1 FLMCR1 is set The erase verify time is not included 4 Programming time maximum value tP MAX wait time after P bit setting z maximum number of writes N 5 Set the maximum number of writes N according to the actual set values of z1...

Page 245: ...eration Timing tOSC VIH VIL tCPH tCPL tCPr OSC1 tCPf Figure 16 1 System Clock Input Timing tREL VIL tREL VIL VCC 0 7 VCC OSC1 Figure 16 2 RES Low Width Timing VIH VIL tIL to FTCI FTIOA to FTIOD TMCIV TMRIV TRGV tIH Figure 16 3 Input Timing ...

Page 246: ...tScyc tTXD tRXS tRXH VOH V or V IH OH V or V IL OL VOL SCK3 TXD transmit data RXD receive data Note Output timing reference levels Output high Output low Load conditions are shown in figure 16 6 V 2 0 V V 0 8 V OH OL Figure 16 5 Serial Interface 3 Synchronous Mode Input Output Timing ...

Page 247: ...Rev 1 0 03 01 page 223 of 280 16 4 Output Load Circuit VCC 2 4 kΩ 12 kΩ 30 pF LSI output pin Figure 16 6 Output Load Condition ...

Page 248: ...Rev 1 0 03 01 page 224 of 280 ...

Page 249: ... CCR V V overflow flag in CCR C C carry flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the o...

Page 250: ...ondition Code Notation Symbol Description Changed according to execution result Undetermined no guaranteed value 0 Cleared to 0 1 Set to 1 Not affected by execution of the instruction Varies depending on conditions described in notes ...

Page 251: ...d MOV W d 16 ERs Rd MOV W d 24 ERs Rd MOV W ERs Rd MOV W aa 16 Rd MOV W aa 24 Rd MOV W Rs ERd MOV W Rs d 16 ERd MOV W Rs d 24 ERd Operation xx 8 Rd8 Rs8 Rd8 ERs Rd8 d 16 ERs Rd8 d 24 ERs Rd8 ERs Rd8 ERs32 1 ERs32 aa 8 Rd8 aa 16 Rd8 aa 24 Rd8 Rs8 ERd Rs8 d 16 ERd Rs8 d 24 ERd ERd32 1 ERd32 Rs8 ERd Rs8 aa 8 Rs8 aa 16 Rs8 aa 24 xx 16 Rd16 Rs16 Rd16 ERs Rd16 d 16 ERs Rd16 d 24 ERs Rd16 ERs Rd16 ERs32 ...

Page 252: ...PE aa 16 Rd MOVTPE Rs aa 16 Operation ERd32 2 ERd32 Rs16 ERd Rs16 aa 16 Rs16 aa 24 xx 32 Rd32 ERs32 ERd32 ERs ERd32 d 16 ERs ERd32 d 24 ERs ERd32 ERs ERd32 ERs32 4 ERs32 aa 16 ERd32 aa 24 ERd32 ERs32 ERd ERs32 d 16 ERd ERs32 d 24 ERd ERd32 4 ERd32 ERs32 ERd ERs32 aa 16 ERs32 aa 24 SP Rn16 SP 2 SP SP ERn32 SP 4 SP SP 2 SP Rn16 SP SP 4 SP ERn32 SP Cannot be used in this LSI Cannot be used in this LS...

Page 253: ... L 4 ERd DEC B Rd DEC W 1 Rd DEC W 2 Rd Operation Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 C Rd8 Rd8 Rs8 C Rd8 ERd32 1 ERd32 ERd32 2 ERd32 ERd32 4 ERd32 Rd8 1 Rd8 Rd16 1 Rd16 Rd16 2 Rd16 ERd32 1 ERd32 ERd32 2 ERd32 Rd8 decimal adjust Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 C Rd8 Rd8 Rs8 ...

Page 254: ...ecimal adjust Rd8 Rd8 Rs8 Rd16 unsigned multiplication Rd16 Rs16 ERd32 unsigned multiplication Rd8 Rs8 Rd16 signed multiplication Rd16 Rs16 ERd32 signed multiplication Rd16 Rs8 Rd16 RdH remainder RdL quotient unsigned division ERd32 Rs16 ERd32 Ed remainder Rd quotient unsigned division Rd16 Rs8 Rd16 RdH remainder RdL quotient signed division ERd32 Rs16 ERd32 Ed remainder Rd quotient signed divisio...

Page 255: ...C xx Rn ERn d ERn ERn ERn aa d PC aa NEG B Rd NEG W Rd NEG L ERd EXTU W Rd EXTU L ERd EXTS W Rd EXTS L ERd 0 Rd8 Rd8 0 Rd16 Rd16 0 ERd32 ERd32 0 bits 15 to 8 of Rd16 0 bits 31 to 16 of ERd32 bit 7 of Rd16 bits 15 to 8 of Rd16 bit 15 of ERd32 bits 31 to 16 of ERd32 B W L W L W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Normal Advanced 0 0 0 0 0 0 NEG EXTU EXTS ...

Page 256: ...x 16 Rd XOR W Rs Rd XOR L xx 32 ERd XOR L ERs ERd NOT B Rd NOT W Rd NOT L ERd Operation Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 B B W W ...

Page 257: ...d ROTXR L ERd ROTL B Rd ROTL W Rd ROTL L ERd ROTR B Rd ROTR W Rd ROTR L ERd B W L B W L B W L B W L B W L B W L B W L B W L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Normal Advanced Addressing Mode and Instruction Length bytes xx Rn ERn d ERn ERn ERn aa d PC aa 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operation MSB LSB 0 C MSB LSB 0 C C MSB LS...

Page 258: ... BTST xx 3 aa 8 BTST Rn Rd BTST Rn ERd BTST Rn aa 8 BLD xx 3 Rd Operation xx 3 of Rd8 1 xx 3 of ERd 1 xx 3 of aa 8 1 Rn8 of Rd8 1 Rn8 of ERd 1 Rn8 of aa 8 1 xx 3 of Rd8 0 xx 3 of ERd 0 xx 3 of aa 8 0 Rn8 of Rd8 0 Rn8 of ERd 0 Rn8 of aa 8 0 xx 3 of Rd8 xx 3 of Rd8 xx 3 of ERd xx 3 of ERd xx 3 of aa 8 xx 3 of aa 8 Rn8 of Rd8 Rn8 of Rd8 Rn8 of ERd Rn8 of ERd Rn8 of aa 8 Rn8 of aa 8 xx 3 of Rd8 Z xx 3...

Page 259: ... BIXOR xx 3 ERd BIXOR xx 3 aa 8 Operation xx 3 of ERd C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of ERd C xx 3 of aa 8 C C xx 3 of Rd8 C xx 3 of ERd24 C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of ERd24 C xx 3 of aa 8 C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of...

Page 260: ... BVC d 8 BVC d 16 BVS d 8 BVS d 16 BPL d 8 BPL d 16 BMI d 8 BMI d 16 BGE d 8 BGE d 16 BLT d 8 BLT d 16 BGT d 8 BGT d 16 BLE d 8 BLE d 16 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 Normal Advanced Addressing Mode and Instruction Length bytes xx Rn ERn d ERn ERn ERn aa d PC aa 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 Operation Always Never C Z 0 C Z 1 C 0 ...

Page 261: ...de I H N Z V C xx Rn ERn d ERn ERn ERn aa d PC aa JMP ERn JMP aa 24 JMP aa 8 BSR d 8 BSR d 16 JSR ERn JSR aa 24 JSR aa 8 RTS Operation PC ERn PC aa 24 PC aa 8 PC SP PC PC d 8 PC SP PC PC d 16 PC SP PC ERn PC SP PC aa 24 PC SP PC aa 8 PC SP 2 2 4 4 2 4 2 2 2 4 6 Normal Advanced 8 6 8 6 8 8 8 10 8 10 8 10 12 10 JMP BSR JSR RTS ...

Page 262: ... 24 ERd STC CCR ERd STC CCR aa 16 STC CCR aa 24 ANDC xx 8 CCR ORC xx 8 CCR XORC xx 8 CCR NOP Operation PC SP CCR SP vector PC CCR SP PC SP Transition to power down state xx 8 CCR Rs8 CCR ERs CCR d 16 ERs CCR d 24 ERs CCR ERs CCR ERs32 2 ERs32 aa 16 CCR aa 24 CCR CCR Rd8 CCR ERd CCR d 16 ERd CCR d 24 ERd ERd32 2 ERd32 CCR ERd CCR aa 16 CCR aa 24 CCR xx 8 CCR CCR xx 8 CCR CCR xx 8 CCR PC PC 2 B B W ...

Page 263: ...own here For other cases see section A 3 Number of Execution States 2 n is the value set in register R4L or R4 1 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 2 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 3 Retains its previous value when the result is zero otherwise cleared to 0 4 Set to 1 when the adjustment produces a carry otherwise retains...

Page 264: ...D B BNE RTE AND LDC BEQ TRAPA BLD BILD BST BIST BVC MOV BPL JMP BMI EEPMOV ADDX SUBX BGT JSR BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV Instruction when most significant bit of BH is 0 Instruction when most significant bit of BH is 1 Instruction code Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 BVS BLT BGE BSR Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Tab...

Page 265: ...V MOV BHI CMP CMP LDC STC BCC OR OR BPL BGT Instruction code BVS SLEEP BVC BGE Table A 2 3 Table A 2 3 Table A 2 3 ADD MOV SUB CMP BNE AND AND INC EXTU DEC BEQ INC EXTU DEC BCS XOR XOR SHLL SHLR ROTXL ROTXR NOT BLS SUB SUB BRN ADD ADD INC EXTS DEC BLT INC EXTS DEC BLE SHAL SHAR ROTL ROTR NEG BMI 1st byte 2nd byte AH BH AL BL SUB ADDS SHLL SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG ...

Page 266: ...R BCLR BCLR DIVXS BTST BTST BTST BTST OR XOR BOR BIOR BXOR BIXOR BAND BIAND AND BLD BILD BST BIST Instruction when most significant bit of DH is 0 Instruction when most significant bit of DH is 1 Instruction code 1 1 1 1 2 2 2 2 BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Notes 1 2 r is the register designation field aa is the absolute address field 1st byte 2nd byte AH BH AL BL 3rd byte CH D...

Page 267: ...cle The total number of states required for execution of an instruction can be calculated by the following expression Execution states I SI J SJ K SK L SL M SM N SN Examples When instruction is fetched from on chip ROM and an on chip RAM is accessed BSET 0 FF00 From table A 4 I L 2 J K M N 0 From table A 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instruction is fetched from...

Page 268: ... Access Location Instruction Cycle On Chip Memory On Chip Peripheral Module Instruction fetch SI 2 Branch address read SJ Stack operation SK Byte data access SL 2 or 3 Word data access SM Internal operation SN 1 Note Depends on which on chip module is accessed See section B 1 Register Addresses ...

Page 269: ...W Rs Rd 1 ADDS ADDS W 1 Rd 1 ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 ...

Page 270: ...xx 3 Rd 2 1 BILD xx 3 aa 8 2 1 BIOR BIOR xx 3 Rd 1 BIOR xx 3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2 1 BOR xx 3 a...

Page 271: ...8 2 1 BTST Rn Rd 1 BTST Rn Rd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 MOV MOV B xx 8 Rd...

Page 272: ... 2 1 MOV B Rs Rd 1 1 MOV B Rs d 16 Rd 2 1 MOV B Rs Rd 1 1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16d 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 ROTL ROTL B...

Page 273: ...2 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL SHLL B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 Rd 1 SUBS W 2 Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 Note n specified value in R4L The source and destination operands are accessed n 1 times respectively ...

Page 274: ... XOR NOT BCC BSR JMP JSR RTS TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP Data transfer instructions Arithmetic operations Logical operations Shift operations Bit manipulations Branching instructions System control instructions Block data transfer instructions BWL BWL WL B B B xx Rn ERn d 16 ERn d 24 ERn ERn ERn aa 8 aa 16 aa 24 d 8 PC d 16 PC aa 8 BWL BWL BWL B L BWL B BW BWL WL BWL BWL BWL B B B BW...

Page 275: ...l register B GRB 16 H FF8A Timer W 16 1 2 General register C GRC 16 H FF8C Timer W 16 1 2 General register D GRD 16 H FF8E Timer W 16 1 2 Flash memory control register 1 FLMCR1 8 H FF90 ROM 8 2 Flash memory control register 2 FLMCR2 8 H FF91 ROM 8 2 Erase block register 1 EBR1 8 H FF93 ROM 8 2 Flash memory enable register FENR 8 H FF9B ROM 8 2 Timer control register V0 TCRV0 8 H FFA0 Timer V 8 3 T...

Page 276: ... 8 H FFC0 WDT 2 8 2 Timer counter WD TCWD 8 H FFC1 WDT 2 8 2 Timer mode register WD TMWD 8 H FFC2 WDT 2 8 2 Address break control register ABRKCR 8 H FFC8 Address break 8 2 Address break status register ABRKSR 8 H FFC9 Address break 8 2 Break address register H BARH 8 H FFCA Address break 8 2 Break address register L BARL 8 H FFCB Address break 8 2 Break data register H BDRH 8 H FFCC Address break...

Page 277: ... 8 2 Port control register 8 PCR8 8 H FFEB I O port 8 2 System control register 1 SYSCR1 8 H FFF0 Power down 8 2 System control register 2 SYSCR2 8 H FFF1 Power down 8 2 Interrupt edge select register 1 IEGR1 8 H FFF2 Interrupts 8 2 Interrupt edge select register 2 IEGR2 8 H FFF3 Interrupts 8 2 Interrupt enable register 1 IENR1 8 H FFF4 Interrupts 8 2 Interrupt flag register 1 IRR1 8 H FFF6 Interr...

Page 278: ...9 GRB8 GRB7 GRB6 GRB5 GRB4 GRB3 GRB2 GRB1 GRB0 GRC GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9 GRC8 GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0 GRD GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9 GRD8 GRD7 GRD6 GRD5 GRD4 GRD3 GRD2 GRD1 GRD0 FLMCR1 SWE ESU PSU EV PV E P ROM FLMCR2 FLER EBR1 EB4 EB3 EB2 EB1 EB0 FENR FLSHE TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V TCSRV CMFB CMFA OVF OS3 OS2 OS1 OS...

Page 279: ...CWE B4WI TCSRWE B2WI WDON B0WI WRST WDT TCWD TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0 TMWD CKS3 CKS2 CKS1 CKS0 ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break ABRKSR ABIF ABIE BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0 BDRH BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0 BDRL BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 B...

Page 280: ...CR22 PCR21 PCR20 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 PCR7 PCR76 PCR75 PCR74 PCR8 PCR84 PCR83 PCR82 PCR81 PCR80 SYSCR1 SSBY STS2 STS1 STS0 Power down SYSCR2 SMSEL DTON MA2 MA1 MA0 IEGR1 IEG3 IEG0 Interrupts IEGR2 WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0 IENR1 IENDT IENWP IEN3 IEN0 IRR1 IRRDT IRRI3 IRRI0 IWPR IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 MSTCR1 MSTS3 MSTAD MSTWD MSTTW MSTTV Power ...

Page 281: ...ed Initialized EBR1 Initialized Initialized Initialized FENR Initialized Initialized Initialized TCRV0 Initialized Initialized Initialized Timer V TCSRV Initialized Initialized Initialized TCORA Initialized Initialized Initialized TCORB Initialized Initialized Initialized TCNTV Initialized Initialized Initialized TCRV1 Initialized Initialized Initialized SMR Initialized Initialized Initialized SCI...

Page 282: ...ed Initialized TCSRWD Initialized WDT TCWD Initialized TMWD Initialized ABRKCR Initialized Address Break ABRKSR Initialized BARH Initialized BARL Initialized BDRH Initialized BDRL Initialized PUCR1 Initialized I O port PUCR5 Initialized PDR1 Initialized PDR2 Initialized PDR5 Initialized PDR7 Initialized PDR8 Initialized PDRB Initialized PMR1 Initialized PMR5 Initialized PCR1 Initialized PCR2 Initi...

Page 283: ...lized Power down SYSCR2 Initialized Power down IEGR1 Initialized Interrupts IEGR2 Initialized Interrupts IENR1 Initialized Interrupts IRR1 Initialized Interrupts IWPR Initialized Interrupts MSTCR1 Initialized Power down MSTCR2 Initialized Power down Note is not initialized WDT Watchdog timer ...

Page 284: ...Block RES goes low in a reset and SBY goes low in a reset and in standby mode PDR PUCR PMR PCR PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register TRGV Internal data bus Pull up MOS Legend Figure C 1 Port 1 Block Diagram P17 ...

Page 285: ...1 page 261 of 280 PDR PUCR PMR PCR PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register Internal data bus Pull up MOS Legend Figure C 2 Port 1 Block Diagram P14 ...

Page 286: ... 0 03 01 page 262 of 280 PDR PUCR PCR PUCR Port pull up control register PDR Port data register PCR Port control register Internal data bus Pull up MOS Legend Figure C 3 Port 1 Block Diagram P16 P15 P12 P10 ...

Page 287: ...Rev 1 0 03 01 page 263 of 280 PDR PUCR PCR PUCR Port pull up control register PDR Port data register PCR Port control register Internal data bus Pull up MOS Legend Figure C 4 Port 1 Block Diagram P11 ...

Page 288: ...Rev 1 0 03 01 page 264 of 280 PDR PMR PCR PMR Port mode register PDR Port data register PCR Port control register Internal data bus TxD SCI3 Legend Figure C 5 Port 2 Block Diagram P22 ...

Page 289: ...Rev 1 0 03 01 page 265 of 280 PDR PCR PDR Port data register PCR Port control register RE Internal data bus RxD SCI3 Legend Figure C 6 Port 2 Block Diagram P21 ...

Page 290: ...Rev 1 0 03 01 page 266 of 280 PDR PCR PDR Port data register PCR Port control register SCKIE Internal data bus SCKI SCI3 SCKOE SCKO Legend Figure C 7 Port 2 Block Diagram P20 ...

Page 291: ...Rev 1 0 03 01 page 267 of 280 PDR PCR PMR PMR Port mode register PDR Port data register PCR Port control register Internal data bus Legend Figure C 8 Port 5 Block Diagram P57 P56 ...

Page 292: ...1 page 268 of 280 PDR PUCR PMR PCR PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register Internal data bus Pull up MOS Legend Figure C 9 Port 5 Block Diagram P55 ...

Page 293: ...ge 269 of 280 PDR PUCR PMR PCR PUCR Port pull up control register PMR Port mode register PDR Port data register PCR Port control register Internal data bus Pull up MOS Legend Figure C 10 Port 5 Block Diagram P54 to P50 ...

Page 294: ...Rev 1 0 03 01 page 270 of 280 PDR PCR OS3 OS2 OS1 OS0 TMOV PDR Port data register PCR Port control register Internal data bus Timer V Legend Figure C 11 Port 7 Block Diagram P76 ...

Page 295: ...Rev 1 0 03 01 page 271 of 280 PDR PCR TMCIV PDR Port data register PCR Port control register Internal data bus Timer V Legend Figure C 12 Port 7 Block Diagram P75 ...

Page 296: ...Rev 1 0 03 01 page 272 of 280 PDR PCR TMRIV PDR Port data register PCR Port control register Internal data bus Timer V Legend Figure C 13 Port 7 Block Diagram P74 ...

Page 297: ...03 01 page 273 of 280 PDR PCR PDR Port data register PCR Port control register Internal data bus FTIOA FTIOB FTIOC FTIOD Timer W Output control signals A to D Legend Figure C 14 Port 8 Block Diagram P84 to P81 ...

Page 298: ...Rev 1 0 03 01 page 274 of 280 PDR PCR FTCI PDR Port data register PCR Port control register Internal data bus Timer W Legend Figure C 15 Port 8 Block Diagram P80 ...

Page 299: ... Retained Retained High impedance P22 to P20 High impedance Functioning Retained Retained High impedance P57 to P50 High impedance Functioning Retained Retained High impedance P76 to P74 High impedance Functioning Retained Retained High impedance P84 to P80 High impedance Functioning Retained Retained High impedance PB3 to PB0 High impedance High impedance High impedance Retained High impedance No...

Page 300: ...dix D Product Code Lineup Package Hitachi Package Code Product Type LQFP 64 FP 64E LQFP 48 FP 48F H8 3672 Flash memory version Standard product HD64F3672FP HD64F3672FX H8 3670 Flash memory version Standard product HD64F3670FP HD64F3670FX ...

Page 301: ... Book has priority Hitachi Code JEDEC EIAJ Mass reference value FP 64E Conforms 0 4 g Unit mm Dimension including the plating thickness Base material dimension M 12 0 0 2 10 48 33 1 16 17 32 64 49 0 22 0 05 0 08 0 5 12 0 0 2 0 10 1 70 Max 0 17 0 05 0 5 0 2 0 8 1 0 1 45 0 10 0 10 1 25 0 20 0 04 0 15 0 04 Figure E 1 FP 64E Package Dimensions ...

Page 302: ...ue FP 48F 0 4 g Dimension including the plating thickness Base material dimension 0 10 0 8 0 50 0 1 0 17 0 05 0 1 0 05 1 65 Max 1 0 12 0 0 2 10 0 32 0 05 0 13 36 25 1 12 37 48 24 13 0 65 12 0 0 2 M 0 30 0 04 1 425 1 45 0 15 0 04 Unit mm Figure E 2 FP 48F Package Dimensions ...

Page 303: ... erasing units 73 Error Protection 86 Hardware Protection 86 Program Program Verify 81 programming units 73 Programming Erasing in User Program Mode 80 Software Protection 86 General Registers 10 I O Ports 89 I O Port Block Diagrams 260 Instruction Set 16 Arithmetic Operations Instructions 18 19 Bit Manipulation Instructions 21 22 Block Data Transfer Instructions 25 Branch Instructions 23 Data Tra...

Page 304: ...PDR8 105 252 255 258 PDRB 108 253 256 258 PMR1 90 253 256 258 PMR5 97 253 256 258 PUCR1 92 252 255 258 PUCR5 99 252 255 258 RDR 156 252 255 257 RSR 156 SCR3 158 251 254 257 SMR 157 251 254 257 SSR 160 252 255 257 SYSCR1 65 253 256 259 SYSCR2 66 253 256 259 TCNT 133 251 254 257 TCNTV 111 251 254 257 TCORA 111 251 254 257 TCORB 111 251 254 257 TCRV0 112 251 254 257 TCRV1 115 251 254 257 TCRW 128 251...

Page 305: ...tion March 2001 Published by Electronic Devices Sales Marketing Group Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2001 All rights reserved Printed in Japan ...

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