Hitachi H8/3670F-ZTAT HD64F3670, Hardware Manual

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Rev. 1.0, 03/01, page 115 of 280
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
10.3.5 Timer Control Register V1(TCRV1)
TCRV1 is an 8-bit read/write register that selects the edge at the TRGV pin, enables TRGV input,
and selects the clock input to TCNTV.
Bit Bit Name Initial Value R/W Description
7
6
5
−
−
−
1
1
1
−
−
−
Reserved
These bits are always read as 1 and cannot be modified.
4
3
TVEG1
TVEG0
0
0
R/W
R/W
TRGV Input Edge Select
These bits select the TRGV input edge.
00: TRGV trigger input is disabled
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
2 TRGE 0 R/W TRGV Input Enable
This bit disables starting counting-up TCNTV by the input
of the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1
−
1
−
Reserved
This bit is always read as 1 and cannot be modified.
0 ICKS0 0 R/W Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 10-2.
10.4 Operation
10.4.1 Timer V operation
1. According to table 10-2, six internal/external clock signals output by prescaler S can be
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 10-2 shows the count timing with an internal clock signal
selected, and figure 10-3 shows the count timing with both edges of an external clock signal
selected.