Harris Platinum HT EL 2000LS, Technical Manual

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4.3.14
VIS_CLK_GATE U18 & AUR_CLK_GATE
U19 Functional Descriptions
IC
PIN TYPE
FUNCTION
1 IN CLOCK TO ALL REGISTERED OUTPUTS
2 IN VISUAL POWER UP COMMAND
3 IN VISUAL POWER DOWN COMMAND
4-13 IN NOT USED
14 OUT DIVIDE BY 16 OF CLOCK PIN 1
15 OUT U/D DELAY COUNTER BIT 1
16 OUT U/D DELAY COUNTER BIT 4
17 OUT U/D DELAY COUNTER BIT 0
18 OUT DIVIDE BY 32 OF CLOCK PIN 1
19 OUT U/D DELAY COUNT BIT 3
20 OUT DIVIDE BY 8 OF CLOCK PIN 1
21 OUT DIVIDE BY 4 OF CLOCK PIN 1
22 OUT DIVIDE BY 2 OF CLOCK PIN 1
23 OUT CLOCK TO UP/DOWN POWER CONTROL
PALs U18 & U19 contain a divide by 32 free running counter
plus a gated one-shot delay repeat clock rate counter called U/D
DELAY COUNTER.
The U/D DELAY COUNTER BITS only change state when the
UP or DOWN button is pressed otherwise the U/D counter rests
at state 0 count. The U/D counter is clocked once each time pin
18 changes (divide by 32 of pin 1) state. Once the U/D counter
reaches the count of 0Dh it stays there until the button is released.
Pin 23 POWER CONTROL clocks the 12 bit UP/DOWN
POWER CONTROL counters when the RAISE or LOWER
button is pressed. The first one-shot pulse is issued when the U/D
counter is at the count of 04h and then repeats the pin 1 clock
rate after U/D counter reaches the count of 0Dh.
4.3.14.1
METER_CLK_GATE U20 Functional Descriptions
IC
PIN TYPE
FUNCTION
1 IN 9.5HZ CLOCK TO ALL REGISTERS
2 IN METER UP COMMAND
3 IN METER DOWN COMMAND
4 IN VISUAL RAISE POWER COMMAND
5 IN VISUAL LOWER POWER COMMAND
6 IN AURAL RAISE POWER COMMAND
7 IN AURAL LOWER POWER COMMAND
8-13 IN NOT USED
14 OUT VISUAL STAY
15 OUT AURAL POWER DOWN
16 OUT VISUAL POWER DOWN
17 OUT VISUAL POWER UP
18 OUT AURAL STAY
19 OUT METER DELAY BIT 2
20 OUT METER DELAY BIT 1
21 OUT METER DELAY BIT 0
22 OUT METER CLOCK
23 OUT AURAL POWER UP
IC U20 contains debounce logic for the raise/lower controls and
the meter up/down plus a 3 bit counter for clocking the meter
select PAL U17. “Debounce” logic is used to change a noisy
switch closure to a defined transition between two logic states.
The 3 bit binary counter divides the 105ms clock on pin 1 by 8
for a 840ms clock rate to U17 METER SELECT PAL when the
meter UP or DOWN button is pressed, otherwise the counter rests
at 0 count.
The RAISE/LOWER COMMANDS are debounced by the
105ms clock and passed on to the POWER UP/DOWN output
pins.
VISUAL STAY output is asserted Hi if neither VISUAL RAISE
or LOWER buttons are pressed. This signal is used by the visual
power control PALs U26 & U27.
AURAL STAY output is asserted Hi if neither AURAL RAISE
or LOWER buttons are pressed. This signal is used by the aural
power control PALs U29 & U30.
4.3.15
METER_SEL U17 Functional Descriptions
See Table 4-1. U17 Functional Descriptions.
4.3.15.1
VIS_UP/DWN_PWR_CTRL U26 & U27
PALs U26 and U27 form a 12 bit up/down counter with halt
protection at both ends so the count will stop at 0000h 0000h
0000h and FFFFh FFFFh FFFFh which allows a total count of
4096. The counter is reset to 0 on power up if the BAT supply is
low enough otherwise the count is remembered from the last
setting. The direction of count is controlled by pins 2 & 3
POWER UP/DOWN controls from U20 and the CLOCK is
supplied by U18-23. The RESET input to pin 4 forces a tri-state
mode on power fail condition to disconnect the output pins from
the IC without power on them. The STAY input pins 8 & 10 hold
the counter at the present state unless the raise or lower button is
pressed.
The VIDEO_LOSS_DELAY* pin 5, FREQ_LOCK* pin 11, and
RMT_MUTE pin 13 are combined to form RF_MUTE* on pin
22. This signal is asserted low to mute and is passed to the visual
and aural rf mute switch U23-13 and U23-12 which opens the
switch causing U24-7 to go to 0 volts.
4.3.16
Visual DAC U25
The visual DAC is placed in the feedback loop of U24-1 to 2
which allows the amplifier gain to be controlled by the binary
number applied to the U25 DAC thereby controlling the output
voltage that U24-1 produces.
4.3.17
Visual Foldback Control
The output of U24-1 is passed through U23-1 to 2 RF MUTE
switch and U23-3 to 4 CW POWER LEVEL switch through R42
to U24-5 VIS_CTRL_BUF where the foldback voltage derived
from the antenna reflected power sample is subtracted from the
visual power level set by the DAC.
4.3.18
AUR_UP/DWN_PWR_CTRL U29 & U30
The aural power control operates the same as the visual except
there is no CW LEVEL switch in the circuit.
Section IV - Theory of Operation
Rev. B: 7/15/02 888-2457-001 4-3
WARNING: Disconnect primary power prior to servicing.