4.4 PCI Interface Signals –Table 1
Name
Type
Description
AD[31:0]
I/O
PCI Address/Data:
AD[31:0] is a multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a
physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The Ibex Peakwill drive all 0s on AD[31:0] during the
address phase of all PCI Special Cycles.
C/BE[3:0]#
I/O
Bus Command and Byte Enables:
The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/
BE[3:0]# define the Byte Enables.
C/BE[3:0]# Command Type
0000b Interrupt Acknowledge
0001b Special Cycle
0010b I/O Read
0011b I/O Write
0110b Memory Read
0111b Memory Write
1010b Configuration Read
1011b Configuration Write
1100b Memory Read Multiple
1110b Memory Read Line
1111b Memory Write and Invalidate
All command encodings not shown are reserved. The Ibex Peak
does not decode reserved values, and therefore will not respond if a
PCI master generates a cycle using one of the reserved values.
