4.4 PCI Interface Signals –Table 6
Name
Type
Description
PCIRST#
O
PCI Reset:
This is the Secondary PCI Bus reset signal. It is a
logical OR of the primary interface PLTRST# signal and the
state of the Secondary Bus Reset bit of the Bridge Control
register (D30:F0:3Eh, bit 6).
PLOCK#
I/O
PCI Lock:
This signal indicates an exclusive bus operation
and may require multiple transactions to complete. Ibex Peak
asserts PLOCK# when it performs non-exclusive transactions
on the PCI bus. PLOCK# is ignored when PCI masters are
granted the bus.
SERR#
I/OD
System Error:
SERR# can be pulsed active by any PCI
device that detects a system error condition. Upon sampling
SERR# active, the Ibex Peak has the ability to generate an
NMI, SMI#, or interrupt.
PME#
I/OD
PCI Power Management Event:
PCI peripherals drive
PME# to wake the system from low-power states S1–S5.
PME# assertion can also be enabled to generate an SCI from
the S0 state. In some cases the Ibex Peak may drive PME#
active due to an internal wake event. The Ibex Peak will not
drive PME# high, but it will be pulled up to VccSus3_3 by an
internal pull-up resistor.
