Getac 9270D Service Manual Download Page 53

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1.6.1 IBEX PEAK-M GPIO Setting Table-2

Name

Pin

Type

Power well

Tolerance

Default

Original Define

HW Function

GPIO19

I/O

Core

GPI

SATA1GP/GPIO19

GPIO19

GPIO20

I/O

Core

Native

PCIECLKRQ2#/GPIO20

PEB_CLKREQ_NEWCARD#

GPIO21

I/O

Core

GPI

SATA0GP/GPIO21

BT_ON#

GPIO22

I/O

Core

GPI

SCLOCK/GPIO22

BIOS_REC

GPIO23

F34

I/O

Core

Native

LDRQ1#/GPIO23

Reserve

GPIO24

H10

I/O

Resume

GPO

GPIO24

SB_MUTE#

GPIO25

I/O

Resume

Native

PCIECLKRQ3#/GPIO25

PCIECLKRQ3

GPIO26

I/O

Resume

Native

PCIECLKRQ4#/GPIO26

PCIECLKRQ4

GPIO27 AB12

I/O

Resume

GPO

GPIO27

GPIO28

V13

I/O

Resume

GPI

GPIO28

GPIO29

I/O

Resume

GPO

SLP_LAN#/GPIO29

PM_SLP_LAN# ( no connection)

GPIO30

I/O

Resume

GPI

SUS_PWR_DN_ACK/GPIO30

SUS_PWR_ACK

GPIO31

I/O

Resume

GPI

ACPRESENT/GPIO31

AC_PRESENT ( no connection)

GPIO32

I/O

Core

GPO/Native CLKRUN#/GPIO32

PM_CLKRUN#

GPIO33

H32

I/O

Core

GPO

HDA_DOCK_EN#/GPIO33

HDA_DOCK_EN#

GPIO34

M11

I/O

Core

GPI

STP_PCI#/GPIO34

GPIO34

GPIO35

I/O

Core

GPO

GPIO35

SB_MB_ID0

GPIO36

AB7

I/O

Core

GPI

SATA2GP/GPIO36

SB_MB_ID1

GPIO37 AB13

I/O

Core

GPI

SATA3GP/GPIO37

SB_MB_ID2

Summary of Contents for 9270D

Page 1: ...1 9 92 270D N B Maintenance 70D N B Maintenance BY Wenrong pu Technical Maintenance Department GTK MTC Jan 2010 R01 SERVICE MANUAL FOR 9270D SERVICE MANUAL FOR SERVICE MANUAL FOR 9270D 9270D ...

Page 2: ...4 Peripheral Components 1 5 Power Management 1 6 Appendix 2 System View and Disassembly 2 1 System View 2 2 Tools Introduction 2 3 System Disassembly 3 Definition Location of Connectors Switches 3 1 Mother Board 4 Pin Descriptions of Ibex Peak M 5 System Block Diagram 3 3 6 40 46 48 51 67 67 70 71 88 88 91 161 ...

Page 3: ...ry Failure 6 6 Keyboard K B or Touch Pad T P Failure 6 7 Hard Disk Drive Failure 6 8 ODD Failure 6 9 USB Ports Failure 6 10 Audio Failure 6 11 LAN Failure 6 12 Card Reader Slot Failure 6 13 Mini Express Wireless Socket Failure 6 14 Express Card Socket Failure 7 Reference Material 162 164 165 166 167 168 169 170 171 172 173 174 175 176 177 179 ...

Page 4: ...atform consists of a processor and the Platform Controller Hub PCH and enables higher performance lower cost easier validation and improved x y footprint Included in this family of processors is an integrated memory controller IMC and integrated I O IIO such as PCI Express and DMI on a single silicon die This singledie solution is known as a monolithic processor The Ibex Peak provides extensive I ...

Page 5: ...igh speed USB 2 0 Host controllers 2 rate matching hubs seven UHCI host controllers Integrated 10 100 1000 Gigabit Ethernet MAC with System Defense System Management Bus SMBus Specification Version 2 0 with additional support for I2C devices Supports Intel High Definition Audio Supports Intel Matrix Storage Technology Supports Intel Trusted Execution Technology Analog and Digital Display ports Ana...

Page 6: ...yboard touch pad Realtek ALC663 High Definition Azalia Audio Codec based multimedia interface includes Built in stereo speaker and woofer Microphone in and headphone out audio jacks There is one communication the RGMII Giga Ethernet PHY to support RJ 45 LAN jack A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Vista to take full advanta...

Page 7: ...hipset 0 MB on board Type DDRIII SO DIMM 1066 1333 MHz Slot 2 SO DIMM Max Size 8GB ATI M96 XT VRAM 1GB No chips 64x16x8 Function Display Interface Azalia Speaker 2 5 W speak x2 3Wx1 Int Mic 1 Other Dolby Home Theater Logo Basic Function Remark CPU Type TDP Display 1680x945 HD 1920x1080 FHD Chipset Memory Graphic Audio ALC633 Vista Criteria ...

Page 8: ... 4 in 1 Card Reader Slot Type MS MS PRO SD MMC Access LED N A Function SDHC Support Spec SATA I F 2 5 9 5mm height HDD Function Structure CBB Compliant SATA I F 12 7mm height ODD Type Super Multi BD Structure CBB Compliant Bezel G BASE Basic Function Remark Express Card USB PCI E Card Reader Storage Device Remark HDD ODD ...

Page 9: ...cost easier validation and improved x y footprint The PCH may also be referred to as Mobile Intel 5 Series Chipset formerly Ibex Peak M Auburndale is designed for the Calpella platform and is offered in an rPGA988A or a BGA1288 package Included in this family of processors is an integrated graphics and memory controller die on the same package as the processor core die This two chip solution of a ...

Page 10: ... Virtualization Technology for Directed I O Intel VT d Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Supplemental Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel HT Technology Intel 64 architecture Execute Disable Bit Intel Turbo Boost Technology ...

Page 11: ... Modules Raw Card A double sided x16 unbuffered non ECC Raw Card B single sided x8 unbuffered non ECC Raw Card C single sided x16 unbuffered non ECC Raw Card D double sided x8 stacked unbuffered non ECC Raw Card F double sided x8 planar unbuffered non ECC DDR3 DRAM Device Technology Standard 1 Gb and 2 Gb technologies and addressing are supported for x16 and x8 devices There is no support for memo...

Page 12: ...guration System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the SO DIMM Modules are populated in each memory channel a number of different configurations can exist Rules for Populating Memory Slots In all modes the frequency of system memory is the lowest frequency of all memory modules placed in the system as determin...

Page 13: ...ware PCI Express NEW 8 PCI Express root ports NEW PCI Express 2 0 specification running at 2 5GT s NEW Ports 1 4 and 5 8 can independently be configured to support eight x1s two x4s two x2s and four x1s or one x4 and four x1 port widths Support for full 2 5 Gb s bandwidth in each direction per x1 lane Module based Hot Plug supported e g ExpressCard ...

Page 14: ...ntegrated Serial ATA Host Controller Up to six SATA ports Data transfer rates up to 3 0 Gb s 300 MB s Integrated AHCI controller External SATA support NEW Port Disable Capability Intel High Definition Audio Interface PCI Express endpoint Independent Bus Master logic for eight general purpose streams four input and four output Support four external Codecs ...

Page 15: ... sampling output Support for ACPI Device USB 2 0 NEW Two USB 2 0 Rate Matching Hubs to replace functionality of UHCI controllers Two EHCI Host Controllers supporting up to fourteen external ports Per Port Disable Capability Includes up to two USB 2 0 High speed Debug Ports Supports wake up from sleeping states S1 S4 Supports legacy Keyboard Mouse software ...

Page 16: ...E 802 3 10 100 1000 Mbps Ethernet Support Jumbo Frame Support Power Management Logic Supports ACPI 3 0b ACPI defined power states processor driven C states ACPI Power Management Timer SMI generation All registers readable restorable for proper resume from 0 V suspend states Support for APM based legacy power management for non ACPI implementations ...

Page 17: ...dependent manageability bus through SMLink interface Supports SMBus 2 0 Specification Host interface allows processor to communicate via SMBus Slave interface allows an internal or external Microcontroller to access system resources Compatible with most two wire components that are also I2C compatible High Precision Event Timers Advanced operating system interrupt scheduling ...

Page 18: ...I Supports up to two SPI devices Supports 20 MHz 33 MHz SPI devices Support up to two different erase granularities Interrupt Controller Supports up to eight PCI interrupt pins Supports PCI 2 3 Message Signaled Interrupts Two cascaded 82C59 with 15 interrupts Integrated I O APIC capability with 24 interrupts Supports Processor System Bus interrupt delivery ...

Page 19: ...r Security Device Trusted Platform Module connected to LPC Package 27 mm x 27 mm FCBGA Desktop Only 27 mm x 25 mm FCBGA Mobile Only 22 mm x 20 mm FCBGA Mobile SFF Only Analog Display Port Digital Display Three Digital Display ports capable of supporting HDMI DVI and Display port One Digital Display port supporting SDVO LVDS ...

Page 20: ... direction 5 GB s concurrent PCI Express Root Ports 1 4 can be statically configured as four x1 Ports or ganged together to form one x4 port Ports 5 and 6 can only be used as two x1 ports Serial ATA SATA Controller The Ibex Peak has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 3 0 GB s 300 MB s The SATA con...

Page 21: ...m management GPIO and RTC Serial Peripheral Interface SPI The Ibex Peak implements an SPI Interface as an alternative interface for the BIOS flash device An SPI flash device can be used as a replacement for the FWH and is required to support Gigabit Ethernet Intel Active Management Technology and integrated Intel Quiet System Technology The Ibex Peak supports up to two SPI flash devices with speed...

Page 22: ...n by off loading communication tasks from the processor Two large configurable transmit and receive FIFOs up to 20 KB each help prevent data underruns and overruns while waiting for bus accesses This enables the integrated LAN controller to transmit data with minimum interframe spacing IFS The LAN controller can operate at multiple speeds 10 100 1000 MB s and in either full duplex or half duplex m...

Page 23: ... On the input side the Ibex Peak adds support for an array of microphones System Management Bus SMBus 2 0 The Ibex Peak contains an SMBus Host interface that allows the processor to communicate with SMBus slaves This interface is compatible with most I2C devices Special I2C commands are implemented The Ibex Peak s SMBus host controller provides a mechanism for the processor to initiate communicati...

Page 24: ... 7 9 11 12 13 Programmable Additive Latency 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 6 1066Mbps 7 1333Mbps 8 1600Mbps 9 1800Mbps 10 2000Mbps 8 bit pre fetch Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe Internal ...

Page 25: ...te of June 01 2008 Featuring three stereo DACs two stereo ADCs legacy analog input to analog output mixing one stereo digital microphone converter and two independent S PDIF output converters to provide a fully integrated audio solution for multimedia desktop and mobile PCs and ultra mobile devices Two stereo ADCs and one stereo digital microphone converter support analog microphone recording and ...

Page 26: ... used to output digital stream to HDMI transmitter is getting more popular in high end multimedia PC Addition to the audio functions ALC663 supports enhanced power management Its power management design is compliant to the latest Intel low power ECR saves more power consumption when audio function is not being used offering wake up for jack detection when system is in power down state which can ex...

Page 27: ...nd clicks noise during power up or shutdown mode operation It also improved the power off pop noise and protects the chip from being destroyed by over temperature and short current failure To simplify the audio system design APA2030 combines a stereo bridge tied loads BTL mode for speaker drive and a stereo single end SE mode for headphone drive into a single chip where both modes are easily switc...

Page 28: ...at VDD 5V BTL RL 4W THD N 0 1 Output Power at 1 THD N 2 6W at VDD 5V BTL RL 3W 2 3W at VDD 5V BTL RL 4W at 10 THD N 3 3W at VDD 5V BTL RL 3W 2 7W at VDD 5V BTL RL 4W Depop Circuitry Integrated Thermal shutdown protection and over current protection circuitry ...

Page 29: ...2 6 Keyboard System IT8512 Universal Keyboard Controller 8032 Embedded Controller Twin Turbo version 3 stage pipeline 9 2 MHz for EC domain and 8032 internal timer Variable frequency range to gain the maximum 8032 code fetch performance Instruction set compatible with standard 8051 2 LPC Bus Interface Compatible with the LPC specification v1 1 Supports I O read write ...

Page 30: ...sh Interface Behaves as a LPC FWH memory device HLPC to the host SouthBridge Supports external serial flash with 32 3 64 5 MHz Up to 16M bytes Flash space shared by the host and EC side serial flash SM Bus Controller SM Bus spec 2 0 3 SM Bus masters 3 SM Bus channels ...

Page 31: ...routing EC Wake Up Control 40 external internal wake up events Interrupt Controller 48 interrupt events to EC Fixed priority Timer Watch Dog Timer 3 16 bit multi function timers inside 8032 which is based on EC clock 1 watch dog timer inside 8032 which is based on EC clock ...

Page 32: ... inside 8032 ACPI Power Management Channel 2 Power management channels Compatible and enhanced mode Battery backed SRAM Supports 64 byte battery backed memory space Supports power switch circuit GPIO Supports 73 port GPIO with serial flash Programmable pull up pull down Schmitt trigger for input ...

Page 33: ... IT8301 chips Each IT8301 supports 38 GPIO ports KBC Interface 8042 style KBC interface Legacy IRQ1 and IRQ12 Fast A20G and KB reset ADC 12 ADC channels 8 external 10 bit resolution 4LSB Digital filter for noise reduction DAC 6 DAC channels 8 bit DAC ...

Page 34: ...olution 8 16 bit common input clock prescaler 4 prescalers for 8 PWM output used for devices with different frequencies 2 Tachometers for measuring fan speed Complete resolution 256 PWM output supported CR256 PS 2 Interface 3 PS 2 interface Hardware Software mode selection ...

Page 35: ...tes at a time using the Page Program instruction The EN25F16 is designed to allow either single Sector at a time or full chip erase operation The EN25F16 can be configured to protect part of the memory as the software protected mode The device can sustain a minimum of 100K program erase cycles on each sector Single power supply operation Full voltage range 2 7 3 6 volt 16 Mbit Serial Flash 16 M bi...

Page 36: ...4 Kbyte Any sector or block can be erased individually Software and Hardware Write Protection Write Protect all or portion of memory viasoftware Enable Disable protection with WP pin High performance program erase speed Page program time 1 5ms typical Sector erase time 150ms typical Block erase time 800ms typical Chip erase time 18 Seconds typical ...

Page 37: ...card reader controller that integrates USB 2 0 Transceiver MCU SIE regulators and memory card access units into a single chip The RTS5159 can support Memory Stick TM Memory Stick Pro TM Memory Stick PRO HG Duo TM Secure Digital TM Multi Media Card TM and xD Picture Card TM but only 1 LUN configuration i e only one of these memory cards can be inserted into RTS5159 system at the same time A serial ...

Page 38: ...0 Support High speed 480Mbps and Full speed 12Mbps Data Transfer USB bus power operation Support Control Bulk IN OUT data pipes Support the following memory card interfaces Secure Digital TM SD MultiMediaCard TM MMC Mini SD Micro SD T flash RS MMC Mobile MMC and MMC micro Memory Stick TM MS Memory Stick PROTM MS PRO MS Duo MS PRO Duo and Micro MS M2 MSPRO HG Duo 8 bit mode xD Picture Card TM xD in...

Page 39: ...rdware CRC Cyclic Redundancy Check function Programmable clock rate for flash memory card interfaces Support MS PRO v1 02 Support MS v1 43 Support MS PRO HG Duo v1 01 Support SD version 2 0 Support MMC version 4 2 ...

Page 40: ...rovide robust transmission and reception capability at high speeds The RTL8111D GR RTL811DL supports Receive Side Scaling RSS to hash incoming TCP connections and load balance received data processing across multiple CPUs RSS improves the number of transactions per second and number of connections per second for increased network throughput The device also features inter connect PCI Express techno...

Page 41: ...e up Audio Volume up Fn F5 LCD external CRT switching Rotate display mode in LCD only CRT only and simultaneously display Fn F6 Brightness down 8 levels Decreases the LCD brightness Fn F7 Brightness up 8 levels Increases the LCD brightness Fn F8 Fn F9 Fn F10 Mute ON OFF Toggle Mute on off Fn F11 Panel ON OFF Toggle Panel on off Fn F12 Suspend to DRAM HDD Force the computer into either Suspend to H...

Page 42: ...ust enable hibernate function in power Management to power button function Continue pushing power button over 4 seconds will force system off at ACPI mode 1 3 3 Cover Switch Hall Sensor System automatically provides power saving by monitoring Cover Switch It will save battery power and prolong the usage time when user closes the notebook cover At ACPI mode there are three functions to be chosen at...

Page 43: ...3 Off 4 Hibernate must enable hibernate function in power management 1 3 4 LED Indicators System has six status LED indicators to display system activity which include six above Front Bezel and MMB LED indicators ...

Page 44: ...n WLAN Enable Blue Off Off Off Left 2 WLAN Disable Off Off Off Off BT BT Enable Blue Off Off Off Left 3 BT Disable Off Off Off Off CAP CAP Enable Blue Off Off Off Left 4 CAP Disable Off Off Off Off Num Lock Num lock Enable Blue Off Off Off Left 5 Num lock Disable Off Off Off Off HDD ODD lock HDD ODD Enable Blue Off Off Off Left 6 HDD ODD Disable Off Off Off Off Power Status Blue Blue Blink Off Off...

Page 45: ...low Battery Warning Capacity below 10 Battery Capacity LED flashes per second system beeps per 2 seconds System will suspend to HDD after 2 Minutes to protect user s data 1 3 5 2 Battery Low State After Battery Warning State and battery capacity is below 5 system will generate beep sound for twice per second 1 3 5 3 Battery Dead State When the battery voltage level reaches 7 4 volts system will sh...

Page 46: ...ature and W83L951AD PWM control fan speed Fan speed is depended on CPU temperature Higher CPU temperature will get faster Fan Speed 1 3 7 CMOS Battery There is a Standard CR2032 3V 220mAh lithium coin battery to supply RTC power When AC in or system main battery inside CMOS battery consumes no power to save coin battery s life cycle ...

Page 47: ...1 4 Peripheral Components 1 4 1 LCD Panel 18 4 SWXGA Glare Non Glare 1 4 2 HDD SATA I F 2 5 9 5mm height HDD 80 100 120 160 GB CBB 1 4 3 ODD SATA I F 12 7mm height ODD Super Multi BlueRay ...

Page 48: ... DDR SO DIMM 0MB DDRII SDRAM memory on board 2 SO DIMM slots for memory expansion 200pin DDRIII 800 1 2 4GB SDRAM SO DIMM Memory Module 1 4 5 Keyboard European keyboard layout 18 45mm key pitch 2 6mm stroke ...

Page 49: ...m Management Mode Full on mode In this mode each device is running with the maximal speed CPU clock is up to its maximum Doze Mode In this mode CPU will be toggling between on stop grant mode either The technology is clock throttling This can save battery power without loosing much computing capability The CPU power consumption and temperature is lower in this mode Standby Mode For more power savi...

Page 50: ...of the system is entering power down mode for more power saving In this mode the following is the status of each device CPU off Twister K Partial off VGA Suspend New Card Suspend Audio off SDRAM self refresh Suspend to HDD All devices are stopped clock and power down ...

Page 51: ...ttery Only Power off Mode The 9270D system has built in Battery only power off mode to prolong the battery usage In this mode Universal Keyboard Controller KBC will be power off In addition the system leakage current shall be less than 0 5mA therefore system power consumption is lower in this mode ...

Page 52: ... GPI TACH2 GPIO6 WLAN_PD GPIO7 J32 I O Core 3V GPI TACH3 GPIO7 SCI GPIO8 F10 I O Resume 3V GPO GPIO8 GPIO8 GPIO9 G16 I O Resume 3V Native USB_OC5 GPIO9 Reserve GPIO10 F12 I O Resume 3V Native USB_OC6 GPIO10 Reserve GPIO11 B9 I O Resume 3V Native SMBALERT GPIO11 GPIO11 GPIO12 K9 I O Resume 3V GPI LAN_PHY_PWR_CTRL GPIO12 GPIO12 GPIO13 J30 I O Resume 3V GPI HAD_DOCK_RST GPIO13 Reserve GPIO14 T15 I O ...

Page 53: ...IECLKRQ3 GPIO26 M9 I O Resume 3V Native PCIECLKRQ4 GPIO26 PCIECLKRQ4 GPIO27 AB12 I O Resume 3V GPO GPIO27 GPIO27 GPIO28 V13 I O Resume 3V GPI GPIO28 GPIO28 GPIO29 F6 I O Resume 3V GPO SLP_LAN GPIO29 PM_SLP_LAN no connection GPIO30 M1 I O Resume 3V GPI SUS_PWR_DN_ACK GPIO30 SUS_PWR_ACK GPIO31 P7 I O Resume 3V GPI ACPRESENT GPIO31 AC_PRESENT no connection GPIO32 Y1 I O Core 3V GPO Native CLKRUN GPIO...

Page 54: ...me 3V Native PCIECLKRQ6 GPIO45 PCIECLKRQ6 GPIO46 F1 I O Resume 3V Native PCIECLKRQ7 GPIO46 PCIECLKRQ7 GPIO47 H1 I O Resume 3V Native PEG_A_CLKRQ GPIO47 M96_CLKREQ GPIO48 AB6 I O Core 3V GPI SDATAOUT1 GPIO48 GPIO48 GPIO49 AA4 I O Core 3V GPI SATA5GP GPIO49 TEMP ALERT Temp_ALERT GPIO50 A46 I O Core 5V Native REQ1 GPIO50 PCI_REQ1 no connection GPIO51 K45 I O Core 3V Native GNT1 GPIO51 PCI_GNT 1 no co...

Page 55: ... GPIO62 E3 I O Resume 3V Native SUSCLK GPIO62 GPIO62 GPIO63 E4 I O Resume 3V Native SLP_S5 GPIO63 SLP_S5 GPIO64 T45 I O Core 3V Native CLKOUTFLEX0 GPIO64 Reserve GPIO65 P43 I O Core 3V Native CLKOUTFLEX1 GPIO65 Reserve GPIO66 T42 I O Core 3V Native CLKOUTFLEX2 GPIO66 Reserve GPIO67 N50 I O Core 3V Native CLKOUTFLEX3 GPIO67 Reserve GPIO72 A6 I O Resume 3V Native BATLOW GPIO72 PM_BATLOW no connectio...

Page 56: ... GPB0 KBC_RX 109 TXD GPB1 KBC_TX 123 CTX0 GPB2 SUSB_1 8VS 110 SMCLK0 GPB3 BAT_CLK 111 SMDAT0 GPB4 BAT_DATA 126 GA20 GPB5 KBC_A20GATE 4 KBRST GPB6 KBC_RCIN 112 RING PWRFAIL LPCRST GPB7 IRQ 119 CRX0 GPC0 SUSB_1 05VS 115 SMCLK1 GPC1 SMBCLK_PCH 116 SMDAT1 GPC2 SMBDATA_PCH 56 KSO16 GPC3 KBC_SB_PWRBTN 120 TMRI0 WUI2 GPC4 SUSB 57 KSO17 GPC5 SB_RSMRST 124 TMRI1 WUI3 GPC6 RESERVE 16 PWUREQ GPC7 KBC_WAKE_UP...

Page 57: ...DD3S 83 EGCS GPE2 SUSB_0 75VS 84 EGCLK GPE3 SUSC_3V 125 PWRSW GPE4 PWRBTN 35 WUI5 GPE5 BAT_TEMP 17 LPCPD WUI6 GPE6 LPC_PD 20 L80LLAT WUI7 GPE7 RESERVE 85 PS2CLK0 GPF0 TP_CLK 86 PS2DAT0 GPF1 TP_DATA 87 PS2CLK1 GPF2 VCCP_PWRGD 88 PS2DAT1 GPF3 KBD_US JP 89 PS2CLK2 WUI20 GPF4 LCD_ENABKL 90 PS2DAT2 WUI21 GPF5 CRT_IN 117 SMCLK2 WUI22 GPF6 SMBCLK_KBC 118 SMDAT2 WUI23 GPF7 SMBDATA_KBC 106 GPG0 SUSB_1 5VS ...

Page 58: ...D5 SUSB_CPU_CORE 99 GPH6 ID6 LEARNING 66 ADC0 GPI0 BAT_VOLT 67 ADC1 GPI1 GND 68 ADC2 GPI2 GND 69 ADC3 GPI3 I LIMIT 70 ADC4 GPI4 KBC_MB_ID_0 71 ADC5 GPI5 KBC_MB_ID_1 72 ADC6 GPI6 KBC_CPUCORE 73 ADC7 GPI7 GND 76 DAC0 GPJ0 I_CTRL 77 DAC1 GPJ1 SUS_PWR_ACK 78 DAC2 GPJ2 PWR_BTN_LED 79 DAC3 GPJ3 DAC_BRIG 80 DAC4 GPJ4 SUSB_VCCP 81 DAC5 GPJ5 SUSB_3VS 1 VSS GND 2 CK32KE CK32KE 3 VBAT GND 5 SERIRQ SERIRQ 6 L...

Page 59: ... 12 VSS GND 13 LPCCLK CLK_PCI_KBC 14 WRST KBC_RESET 26 VSTBY VDD3 27 VSS GND 36 KSO0 PD0 KO0 37 KSO1 PD1 KO1 38 KSO2 PD2 KO2 39 KSO3 PD3 KO3 40 KSO4 PD4 KO4 41 KSO5 PD5 KO5 42 KSO6 PD6 KO6 43 KSO7 PD7 KO7 44 KSO8 ACK KO8 45 KSO9 BUSY KO9 46 KSO10 PE KO10 49 VSS GND 50 VSTBY VDD3 51 KSO11 ERR KO11 52 KSO12 SLCT KO12 53 KSO13 KO13 ...

Page 60: ...I1 60 KSI2 INIT KI2 61 KSI3 SLIN KI3 62 KSI4 KI4 63 KSI5 KI5 64 KSI6 KI6 65 KSI7 KI7 74 AVCC VDD3_ALW 75 AVSS ITE_GND 91 VSS GND 92 VSTBY VDD3 101 FSCE KBC_SPI_SCSI 102 FMOSI KBC_SPI_MOSI 103 FMISO KBC_SPI_MISO 105 FSCK KBC_SPI_SCK 113 VSS GND 114 VSTBY VDD3 121 VSTBY VDD3 122 VSS GND 127 VSTBY VDD3 128 CK32K CK32KE ...

Page 61: ...Brand Phoenix Size of EEPROM TBD BIOS Architecture Others Brand Model Name North Bridge None Brand Model Name South Bridge Ibex Peak Chipset Others Module Type DDRIII SO DIMM Module Size 1G 2G Number of Pins 200 Speed 800 1066 MHz On Board Memory Size 0 Number of Slot 2 Form Factor 1 25 inch height Maximum Capacity 8GB Assembling Capability Distribution configurable CPU System BIOS Chipset Memory ...

Page 62: ...DRIII No of Vram Chips 8 pcs Local VRAM Size 1GB 64 x 16 x 8pc UMA VRAM Size Others Interface SATA Height 12 7mm Type Super Multi BD Bezel Type G BASE Others CBB Compliant Assembling Capability Distribution configurable Interface SATA Height Diameter 9 5mm 2 5 RPM 5400 Capacity Others CBB Compliant Assembling Capability Able to assemble at distribution center VIDEO CONTROLLER VRAM Optical Disk Dri...

Page 63: ...I Others Type Underplastic touchpad without scroll bar Number of Button 2 Others Gesture version Type New Card Type II 54mm Interface PCIE USB Number of Slot 1 Interface Azalia Output Channels 5 1 analog output Speaker Two 2 5W stereo speaker Subwoofer 3W Volume Control keyboard function key Internal Microphone x 1 Others DISPLAY KEYBOARD POINTING DEVICE PC Card slot Audio System ...

Page 64: ...Pro MMC Others USB 3 USB 2 0 USB e SATA 1 RJ 11 N A RJ 45 1 Headphone 1 S PDIF 1 Microphone 1 Line In N A DC Input 1 Analog VGA Port 1 DVI D N A DVI I N A S Video Out N A S Video In N A IEEE1394 N A TV in Connector N A IrDA N A CIR N A HDMI 1 Kensington Lock 1 Others N A Memory Card Reader I O Port ...

Page 65: ...ck num lock HDD ODD Interface N A Type Speed Form Factor Assembling Capability Others Interface LAN Phy Speed 10 100 1000 Mbps Interface PCIE USB Form Factor Mini PCIE half size Type B G N Others Assembling Capability Form Factor N A Interface Tuner Others Interface USB Version 2 1 EDR Others TV Card Bluetooth Indicator Modem LAN Wireless LAN Quick Key ...

Page 66: ...0W 120W Input Voltage 100V 240V Output Voltage 19V number of Pin 2 3 D C jack Dimension 2 5mm 5 5MM 11 5 12 5mm Others 2 5mm 5 5MM 11 5 12 5mm Dimensions L x W x D mm W441 x D298 5 x H 25 39mm Weight Kg 3 7KG Other Specifications a Webcam USB 2 0 interface 1 3M Other Specifications C RF Receiver option USB interface AC Adapter Battery Other Specifications b MMB module 6 touch sense buttons TBD Med...

Page 67: ...1 6 3 9270D Product Spec 7 ITEM CATEGORY DESCRIPTION Microsoft LOGO Windows Logo Vista Premium SP1 Windows 7 Regulation EMC CE Safety CB Green Product Coverage ROHS Yes ...

Page 68: ...sassembly 2 1 System View 2 1 1 Left side View RJ45 Connector ESATA USB Connector Kensington Lock HDMI Connector n o p r q CRT Connector USB Ports Card Reader Connector z 6 z 7 z 8 Express Card Connector n o p q r s t z 8 ...

Page 69: ...2 1 2 Right side View n o p q rs SPDIF Connector Headphone out ODD n o p q MIC In USB Port r Power Jack z 6 2 1 3 Rear View n Ventilation Openings n ...

Page 70: ...2 1 4 Bottom View Z o n n HDD CPU DDR3 SO DIMM Mini Express Card Battery Park o p q n o p r 2 1 5 Top open View n LCD Screen o p Internal MIC Power Button Touch Pad q Keyboard r s t Speaker Web Camera ...

Page 71: ...troduction 1 Minus screw driver for notebook assembly disassembly 2 mm 2 mm 2 Auto screw driver for notebook assembly disassembly Bit Size 0 Screw Size Tooling Tor Bit Size 1 M2 0 Auto Screw driver 2 0 2 5 kg cm2 0 ...

Page 72: ...k NOTE Before you start to install replace these modules disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power Modular Components LCD Assembly Components NOTEBOOK 2 3 1 Battery Pack 2 3 2 CPU 2 3 3 DDR2 SDRAM 2 3 4 HDD 2 3 5 ODD 2 3 6 Keyboard 2 3 7 LCD Assembly 2 3 8 Inverter Board 2 3 9 LCD Panel 2 3 10 Audio Jack Board 2 3 11 ODD Transfer Board 2...

Page 73: ...o the unlock position n while take the battery pack out of the compartment o Figure 2 1 o n Figure 2 1 Remove the battery pack 1 Replace the battery pack into the compartment The battery pack should be correctly connected when you hear a clicking sound 2 Slide the release lever to the lock position Reassembly ...

Page 74: ...Remove eight screws fastening the CPU cover Figure 2 2 3 Remove six spring screws that secure the heatsink upon the CPU and remove three screws fastening the fan then disconnect the fan s power cord from system board Figure 2 3 Figure 2 2 Remove eight screws Figure 2 3 Free the heatsink ...

Page 75: ...head corner of the CPU with the beveled corner of the socket then insert CPU pins into the holes Tighten the screw by a flat screwdriver to locking the CPU 2 Connect the fan s power cord to the system board fit the fan and heatsink upon the CPU and secure with nine screws 3 Replace the CPU cover and secure with eight screws 4 Replace the battery pack Refer to section 2 3 1 Reassembly ...

Page 76: ...l the retaining clips outwards n and remove the SO DIMM o Figure 2 5 1 To install the DDR3 match the DDR3 s notched part with the socket s projected part and firmly insert the SO DIMM into the socket at 20 degree angle Then push down until the retaining clips lock the DDR3 into position 2 Replace the CPU cover and secure with eight screws Refer to step 3 of section 2 3 3 Reassembly 3 Replace the b...

Page 77: ... HDD cover Figure 2 6 3 Lift the HDD module out and disconnect the HDD connector Figure 2 7 Figure 2 7 Remove HDD module Figure 2 6 Remove HDD cover Reassembly 1 Reconnect the HDD connector and replace the HDD module to the HDD shielding 2 Replace the HDD compartment cover and secure with two screws 3 Replace the battery pack Refer to section 2 3 1 Reassembly ...

Page 78: ... 2 9 3 Insert a small rod such as a straightened paper clip into ODD s manual eject hole n and push firmly to release the tray Then gently pull out the ODD by holding the tray that pops out o Figure 2 9 n o Figure 2 9 Remove the ODD Reassembly 1 Push the ODD into the compartment and secure with one screw 2 Replace the battery pack Refer to section 2 3 1 Reassembly ...

Page 79: ... Refer to section 2 3 1 Disassembly 2 Remove four screws fastening the keyboard cover then remove the keyboard cover figure 2 10 3 Remove three screws fastening the keyboard Figure 2 11 Figure 2 10 Remove the keyboard cover Figure 2 11 Remove four screws ...

Page 80: ...e keyboard Figure 2 12 Figure 2 12 Remove the keyboard Reassembly 1 Reconnect the keyboard cable and fit the keyboard back into place then secure the keyboard with three screws 2 Replace the keyboard cover and secure with four screws 3 Replace the battery pack Refer to section 2 3 1 Reassembly ...

Page 81: ... 3 1 2 3 6 Disassembly 2 Remove twenty seven screws and disconnect one cable Figure 2 13 3 Turn over the unit remove nine screws and disconnect the touch pad cable then remove the top cover Figure 2 14 Figure 2 13 Remove twenty seven screws and disconnect one cable Figure 2 14 Remove the top cover ...

Page 82: ...to the base unit and secure with nine screws Reconnect the antenna wires and two cables 2 Reconnect the antenna wires and two cables 3 Replace the top cover and reconnect the touchpad cable secure with nine screws 4 Turn over the unit reconnect one cable and secure with twenty seven screws 3 Replace the keyboard ODD HDD DDR3 CPU and battery pack Refer to sections 2 3 6 2 3 1 Reassembly ...

Page 83: ...Figure 2 16 3 Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out Repeat the process as figure 1 20 arrowhead hints until the cover is completely separated from the housing 4 Remove nine screws then separate panel from LCD housing Figure 2 17 Figure 2 16 Remove LCD cover Figure 2 17 Remove nine screws ...

Page 84: ...ove the inverter board Reassembly 1 Replace the inverter board and reconnect two cables 2 Replace the LCD panel and inverter board into the LCD housing then secure with nine screws 3 Fit the LCD cover and secure with six screws 4 Replace the LCD assembly See sections 2 3 7 Reassembly ...

Page 85: ... LCD brackets Figure 2 19 3 Disconnect LCD cable to free the panel Figure 2 20 Figure 2 19 Remove eight screws Figure 2 20 Free the LCD panel Reassembly 1 Replace the cable to the LCD panel 2 Attach the LCD panel s brackets back to LCD panel and secure with eight screws 3 Replace the inverter board and LCD assembly See sections 2 3 8 and 2 3 7 Reassembly ...

Page 86: ...ure 2 21 3 Remove one screw and disconnect two cables then remove the audio jack board Figure 2 22 Figure 2 21 Remove the shielding Figure 2 22 Remove the audio jack board Reassembly 1 Replace the audio jack board and reconnect two cables then secure with one screw 2 Replace the shielding and secure with six screws 3 Replace the LCD assembly See sections 2 3 7 Reassembly ...

Page 87: ...n 2 3 10 Disassembly 3 Remove one screw fastening the ODD transfer board the remove it flatly Figure 2 23 Figure 2 23 Remove the ODD transfer board Reassembly 1 Replace the ODD transfer board flatly and secure with one screw 2 Replace the shielding See step 2 of section 2 3 10 Reassembly 3 Replace the LCD assembly See sections 2 3 7 Reassembly ...

Page 88: ...ning the HDD cable and disconnect two cables the free the system board Figure 2 25 Figure 2 25 Free the system board Figure 2 24 Remove five screws Reassembly 1 Replace the system board and reconnect two cables then secure the HDD cable with two screws 2 Replace the system board into the housing and secure with three screws 3 Replace the ODD transfer board audio jack board and LCD assembly See sec...

Page 89: ...r J703 RJ45 Connector J704 CPU Fan Connector J705 HDMI Connector J706 Internal Subwoofer Connector J707 J708 DDR3 Sockets J709 E SATA USB Connector J710 J713 USB Ports J711 SATA ODD Connector J712 MMB Board Connector J714 MINI Wireless LAN Socket J715 SATA HDD Connector J716 Cardreader Connector PJ701 J702 PJ702 J706 J711 J715 J714 J707 J708 J716 J713 J712 J710 J709 J705 J703 J701 J704 ...

Page 90: ...3 Definition Location of Major Components 3 1 Mother Board Side A 2 U705 U704 U712 U704 NVIDIA M96 PRO U705 Intel Arrandle CPU Socket U712 IBEX PEAK M PM55 ...

Page 91: ...4 J5 J9 J10 U16 J1 LCD Cable Connector J2 Internal Speaker Connector J3 Internal Keyboard Connector J4 Internal Touch pad Connector J5 Bluetooth Board Connector J9 Audio Board Connector J10 Express Card Slot SW1 Power Button SW2 Touch pad Left Button SW3 Touch pad Right Button U16 KBC IT8502J ...

Page 92: ...N I Digital Media Interface Differential Receive Pair 1 DMI0RXP DMI3RXN O Digital Media Interface Differential Transmit Pair 2 DMI0RXP DMI4RXN I Digital Media Interface Differential Receive Pair 2 DMI0RXP DMI5RXN O Digital Media Interface Differential Transmit Pair 3 DMI0RXP DMI6RXN I Digital Media Interface Differential Receive Pair 3 DMI0RXP DMI7RXN I Impedance Compensation Input Determines DMI ...

Page 93: ...ial Receive Pair 1 PETp2 PETn2 O PCI Express Differential Transmit Pair 2 PERp2 PERn2 I PCI Express Differential Receive Pair 2 PETp3 PETn3 O PCI Express Differential Transmit Pair 3 PERp3 PERn3 I PCI Express Differential Receive Pair 3 PETp4 PETn4 O PCI Express Differential Transmit Pair 4 PERp4 PERn4 I PCI Express Differential Receive Pair 4 ...

Page 94: ...al Receive Pair 6 PERp6 PERn7 O PCI Express Differential Transmit Pair 7 NOTE Port 7 may not be available in all Ibex Peak SKUs PERp6 PERn8 I PCI Express Differential Receive Pair 7 NOTE Port 7 may not be available in all Ibex Peak SKUs PERp6 PERn9 O PCI Express Differential Transmit Pair 8 NOTE Port 7 may not be available in all Ibex Peak SKUs PERp6 PERn10 I PCI Express Differential Receive Pair ...

Page 95: ...These signals are multiplexed with the LPC address signals FWH4 LFRAME O Firmware Hub Signals This signal is multiplexed with the LPC LFRAME signal INIT3_3V O Initialization 3 3 V INIT3_3V is asserted by the Ibex Peak for 16 PCI clocks to reset the processor This signal is intended for Firmware Hub ...

Page 96: ...ls are multiplexed on the same PCI pins During the address phase of a transaction C BE 3 0 define the bus command During the data phase C BE 3 0 define the Byte Enables C BE 3 0 Command Type 0000b Interrupt Acknowledge 0001b Special Cycle 0010b I O Read 0011b I O Write 0110b Memory Read 0111b Memory Write 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1110b Memory Re...

Page 97: ...PCI bus DEVSEL is tri stated from the leading edge of PLTRST DEVSEL remains tri stated by the Ibex Peak until driven by a target device FRAME I O Cycle Frame The current initiator drives FRAME to indicate the beginning and duration of a PCI transaction While the initiator asserts FRAME data transfers continue When the initiator negates FRAME the transaction is in the final data phase FRAME is an i...

Page 98: ...e Ibex Peak is an initiator IRDY remains tri stated by the Ibex Peak until driven by an initiator TRDY I O Target Ready TRDY indicates the Ibex Peak s ability as a target to complete the current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed when both TRDY and IRDY are sampled asserted During a read TRDY indicates that the Ibex Peak as a target has pl...

Page 99: ... bits regardless of the valid byte enables The Ibex Peak generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase The Ibex Peak drives and tri states PAR identically to the AD 31 0 lines except that the Ibex Peak delays PAR by exactly one PCI clock PAR is an output during the address phase delayed one clock for all Ib...

Page 100: ...p to 4 masters on the PCI bus REQ 3 1 pins can instead be used as GPIO GNT0 GNT1 GPIO51 GNT2 GPIO53 GNT3 GPIO55 O PCI Grants The Ibex Peak supports up to 4 masters on the PCI bus GNT 3 1 pins can instead be used as GPIO Pull up resistors are not required on these signals If pull ups are used they should be tied to the Vcc3_3 power rail NOTE GNT 3 0 are sampled as a functional strap See Section 4 3...

Page 101: ...ransactions on the PCI bus PLOCK is ignored when PCI masters are granted the bus SERR I OD System Error SERR can be pulsed active by any PCI device that detects a system error condition Upon sampling SERR active the Ibex Peak has the ability to generate an NMI SMI or interrupt PME I OD PCI Power Management Event PCI peripherals drive PME to wake the system from low power states S1 S5 PME assertion...

Page 102: ...ller 1 SATA1TXP SATA1TXN O Serial ATA 1 Differential Transmit Pair These are outbound high speed differential signals to Port 1 In compatible mode SATA Port 1 is the secondary master of SATA Controller 1 SATA1RXP SATA1RXN I Serial ATA 1 Differential Receive Pair These are inbound high speed differential signals from Port 1 In compatible mode SATA Port 1 is the secondary master of SATA Controller 1...

Page 103: ...oller 1 NOTE SATA Port 3 may not be available in all PCH SKUs SATA3RXP SATA3RXN I Serial ATA 3 Differential Receive Pair These are inbound high speed differential signals from Port 3 In compatible mode SATA Port 3 is the secondary slave of SATA Controller 1 NOTE SATA Port 3 may not be available in all PCH SKUs SATA4TXP SATA4TXN O Serial ATA 4 Differential Transmit Pair These are outbound high spee...

Page 104: ...TA Compensation Input Connected to SATAICOMPO on the board SATA0GP GPIO21 I Serial ATA 0 General Purpose This is an input pin which can be configured as an interlock switch corresponding to SATA Port 0 When used as an interlock switch status indication this signal should be drive to 0 to indicate that the switch is closed and to 1 to indicate that the switch is open If interlock switches are not r...

Page 105: ...LED When active the LED is on When tri stated the LED is off An external pull up resistor to Vcc3_3 is required SCLOCK GPIO22 OD O SGPIO Reference Clock The SATA controller uses rising edges of this clock to transmit serial data and the target uses the falling edge of this clock to latch data If SGPIO interface is not used this signal can be used as a GPIO SLOAD GPIO38 OD O SGPIO Load The controll...

Page 106: ...AME FWH4 O LPC Frame LFRAME indicates the start of an LPC cycle or an abort LDRQ0 LDRQ1 GPIO23 I LPC Serial DMA Master Request Inputs LDRQ 1 0 are used to request DMA or bus master access These signals are typically connected to an external Super I O device An internal pull up resistor is provided on these signals LDRQ1 may optionally be used as GPIO ...

Page 107: ...he following fashion PIRQA is connected to IRQ16 PIRQB to IRQ17 PIRQC to IRQ18 and PIRQD to IRQ19 This frees the legacy interrupts PIRQ H E GPIO 5 2 I OD PCI Interrupt Requests In non APIC mode the PIRQx signals can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 Each PIRQx line has a separate Route Control register In APIC mode these signals are connected to the internal I O APIC in the fol...

Page 108: ...rential pairs are used to transmit data address command signals for ports 2 and 3 These ports can be routed to UHCI controller 2 or the EHCI controller 1 NOTE No external resistors are required on these signals The Ibex Peak integrates 15 kΩ pull downs and provides an output driver impedance of 45 Ω which requires no external series resistor USBP4P USBP4N USBP5P USBP5N I O Universal Serial Bus Por...

Page 109: ...ial pairs are used to transmit Data Address Command signals for ports 8 and 9 These ports can be routed to UHCI controller 5 or the EHCI controller 2 NOTE No external resistors are required on these signals The Ibex Peak integrates 15 kΩ pull downs and provides an output driver impedance of 45 Ω which requires no external series resistor USBP10P USBP10N USBP11P USBP11N I O Universal Serial Bus Por...

Page 110: ...C1 GPIO40 OC2 GPIO41 OC3 GPIO42 OC4 GPIO43 OC5 GPIO9 OC6 GPIO10 OC7 GPIO14 I Overcurrent Indicators These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred OC 7 0 may optionally be used as GPIOs NOTES 1 OC pins are not 5 V tolerant 2 OC pins must be shared between ports 3 OC 3 0 can only be used for EHCI controller 1 4 OC 4 7 can only be u...

Page 111: ... PLTRST is in the VccSus3_3 well THRMTRIP I Thermal Trip When low this signal indicates that a thermal trip from the processor occurred and the Ibex Peak will immediately transition to a S5 state The Ibex Peak will not wait for the processor stop grant cycle since the processor has overheated SLP_S3 O S3 Sleep Control SLP_S3 is for power plane control This signal shuts off power to all non critica...

Page 112: ...cates that the Hanksville PHY device must be powered When SLP_LAN is asserted power can be shut off to the Hanksville PHY device SLP_LAN will always be deasserted in S0 and anytime SLP_M is deasserted SLP_LAN behavior in Sx Moff can be configured by ME FW If ME FW is not configuring SLP_LAN host can control the signal behavior by configuring GPIO29 as an output If neither ME FW nor host BIOS confi...

Page 113: ...must not glitch even if RSMRST is low MEPWROK I Management Engine Power OK When asserted indicates that power to the ME subsystem is stable PWRBTN I Power Button The Power Button will cause SMI or SCI to indicate a system request to go to a sleep state If the system is already in a sleep state this signal will cause a wake event If PWRBTN is pressed for more than 4 seconds this will cause an uncon...

Page 114: ...is in reset This signal must remain asserted until at least 1 ms after the LAN power well VccLAN and ME power well VccME3_3 are valid Also LAN_RST must assert a minimum of 40 ns before the LAN power rails become inactive When deasserted this signal is an indication that LAN power wells are stable Note 1 If Intel LAN is enabled LAN_RST must be connected to the same source as MEPWROK 2 If Intel LAN ...

Page 115: ... to powered off planes Pin may also be used as GPIO61 SUSCLK GPIO62 O Suspend Clock This clock is an output of the RTC generator circuit to use by other chips for refresh clock Pin may also be used as GPIO62 DRAMPWRO K O DRAM Power OK This signal should connect to the Processor s SM_DRAMPWROK pin The PCH asserts this pin to indicate when DRAM power is on NOTES 1 This pin should have External pull ...

Page 116: ...RE well of the Ibex Peak is stable SYS_PWROK is used to inform the Ibex Peak that power is stable to some other system component s and the system is ready to start the exit from reset The particular component s associated with SYS_PWROK can vary across platform types supported by the same generation of Ibex Peak Depending on the platform the Ibex Peak may expect and wait for SYS_PWROK at different...

Page 117: ...m the keyboard controller The signal acts as an alternative method to force the A20M signal active It saves the external OR gate needed with various other copyists PROCPWRGD O Processor Power Good This signal should be connected to the processor s VCCPWRGOOD_1 and VCCPWRGOOD_0 input to indicate when the processor power is valid 4 1 11 SM Bus Interface Signals Name Type Description SMBDATA I OD SMB...

Page 118: ...quired SML0ALERT GPIO60 O OD SMLink Alert 0 Output of the integrated LAN controller to external PHY External pull up resistor is required This signal can instead be used as a GPIO60 SML1ALERT GPIO74 O OD SMLink Alert 1 Alert for the ME SMBus controller to optional Embedded Controller or BMC External pull up resistor is required This signal can instead be used as a GPIO74 SML1CLK GPIO58 I OD System...

Page 119: ...1 This signal is connected to the 32 768 kHz crystal If no external crystal is used then RTCX1 can be driven with the desired clock rate RTCX2 Special Crystal Input 2 This signal is connected to the 32 768 kHz crystal If no external crystal is used then RTCX2 should be left floating ...

Page 120: ... is a weak integrated pull down resistor on SPKR pin RTCRST I RTC Reset When asserted this signal resets register bits in the RTC well NOTES 1 Unless CMOS is being cleared only to be done in the G3 power state the RTCRST input must always be high when all other RTC power planes are on 2 In the case where the RTC battery is dead or missing on the platform the RTCRST pin must rise before the RSMRST ...

Page 121: ...r the Ibex Peak This signal has a weak internal pull down resistor HDA_SDO O Intel High Definition Audio Serial Data Out Serial TDM data output to the codec s This serial output is double pumped for a bit rate of 48 Mb s for Intel High Definition Audio NOTE This signal is sampled as a functional strap See Section 4 30 for more details There is a weak integrated pull down resistor on this pin HDA_S...

Page 122: ...ocking switch electrically connects the Intel HD Audio dock signals to the corresponding Ibex Peak signals This signal can instead be used as GPIO33 NOTE This signal is sampled as a functional strap See Section 4 30for more details HDA_DOCK_ RST GPIO13 O High Definition Audio Dock Reset This signal is a dedicated HDA_RST signal for the codec s in the docking station Aside from operating independen...

Page 123: ...al data that connects to a Wireless LAN Device supporting Intel Active Management Technology 4 1 17 Serial Peripheral Interface SPI Signals Name Type Description SPI_CS0 O SPI Chip Select 0 Used as the SPI bus request signal SPI_CS1 O SPI Chip Select 1 Used as the SPI bus request signal SPI_MISO I SPI Master IN Slave OUT Data input pin for Ibex Peak SPI_MOSI O SPI Master OUT Slave IN Data output p...

Page 124: ...this signal is programmable The output default is low These signals are 5V tolerant TACH0 Desktop Only GPIO17 TACH1 Desktop Only GPIO1 TACH2 Desktop Only GPIO6 TACH3 Deskto p Only GPIO7 I Fan Tachometer Inputs Tachometer pulse input signal that is used to measure fan speed This signal is connected to the Sense signal on the fan Can instead be used as a GPIO SST I O Simple Serial Transport Single w...

Page 125: ...ata are received by the test logic at TDI JTAG_TDO I O Test Data Output TDO TDO is the serial output for test instructions and data from the test logic defined in this standard TRST I O Test Reset RST RST is an active low asynchronous signal that can reset the Test Access Port TAP controller Note The RST signal is optional per the IEEE 1149 1 specification and is not functional for Boundary Scan T...

Page 126: ...chronous mode During read operations NAND controller latches input data from NV_IO on the rising and falling edges of NV_DQS During write operations NAND controller outputs data on NV_DQ edge aligned to the rising and falling edges of NV_DQS NV_DQS 0 is the data strobe for the lower data byte NV_DQ 7 0 NV_DQS 1 is the data strobe for the upper data byte NV_DQ 15 8 NOTE These signals are unused in ...

Page 127: ...en any Chip Enable NV_CE 3 0 is asserted Asynchronous Interface Write Enable The active low signal indicates command address or data are driven valid by the PCH NAND controller on the NV_IO bus NV_RB I Ready Busy Indicates the status of the NAND device Ready Busy signals from multiple NAND devices must be wired OR together to provide a single Ready Busy input to NAND controller NV_RCOMP I O NAND B...

Page 128: ...T_DP_N CLKOUT_BCLK1_N O 120 MHz Differential output for DisplayPort reference or 133MHz Differential output to Processor CLKIN_DMI_P CLKIN_DMI_N I 100 MHz differential reference clock from a clock chip in Buffer Through Mode Note This input clock is required to be PCIe 2 0 jitter spec compliant from a clock chip for PCIe 2 0 discrete Graphics platforms CLKOUT_DMI_P CLKOUT_DMI_N O 100MHz Gen2 speci...

Page 129: ...le ended 14 31818MHz reference clock driven by a clock chip CLKOUT_PEG_A_P CLKOUT_PEG_A_N O 100MHz Gen2 specification differential output to PCI Express Graphics device CLKOUT_PEG_B_P CLKOUT_PEG_B_N O 100MHz Gen2 specification differential output to a second PCI Express Graphics device PEG_A_CLKRQ GPIO47 PEG_B_CLKRQ GPIO56 I Clock Request Signals for PEG SLOTS Can instead by used as GPIOs CLKOUT_P...

Page 130: ... GPIO46 I Clock Request Signals for PCI Express 100 MHz Clocks Can instead by used as GPIOs NOTE External Pull up Resistor required if used for CLKREQ functionality CLKOUT_PCI 4 0 O Single Ended 33 3MHz outputs to PCI connectors devices One of these signals must be connected to CLKIN_PCILOOPBACK to function as a PCI clock loopback This allows skew control for variable lengths of CLKOUT_PCI 4 0 ...

Page 131: ...tput to SIO DC Output logic 0 NOTE Default clock setting requires no ME FW configuration CLKOUTFLEX2 GPIO66 O Configurable as a GPIO or as an Intel Management Firmware programmable output clock which can be configured as one of the following 33 MHz 14 31818 MHz Default DC Output logic 0 NOTE Default clock setting requires no ME FW configuration CLKOUTFLEX3 GPIO67 O Configurable as a GPIO or as an ...

Page 132: ...annel A differential clock output positive LVDSA_CLK O LVDS Channel A differential clock output negative LVDSB_DATA 3 0 O LVDS Channel B differential data output positive LVDSB_DATA 3 0 O LVDS Channel B differential data output negative LVDSB_CLK O LVDS Channel B differential clock output positive LVDSB_CLK O LVDS Channel B differential clock output negative L_DDC_CLK I O EDID support for flat pan...

Page 133: ...ontrol enable control for LVDS This signal is also called VDD_DBL in the CPIS specification and is used to control the VDC source to the panel logic L_BKLTEN I O LVDS Backlight Enable Panel backlight enable control for LVDS This signal is also called ENA_BL in the CPIS specification and is used to gate power into the backlight circuitry L_BKLTCTL I O Panel Backlight Brightness Control Panel bright...

Page 134: ...nternal color palette DAC DAC_IREF I O A Resistor Set Set point resistor for the internal color palette DAC A 1 kohm 1 resistor is required between DAC_IREF and motherboard ground CRT_HSYNC O HVCMOS CRT Horizontal Synchronization This signal is used as the horizontal sync polarity is programmable or sync interval 2 5 V output CRT_VSYNC O HVCMOS CRT Vertical Synchronization This signal is used as t...

Page 135: ...splay Link 2 positive data in FDI_RXN 7 4 I Display Link 2 negative data in FDI_FSYNC 1 O Display link 2 Frame sync FDI_LSYNC 1 O Display link 2 Line sync FDI_INT O Used for Display interrupts from Ibex Peak to processor 4 1 25 Misc HV Display Signals Name Type Description L_CLKCTLA I O Can be used to control external clock chip for SSC optional SMBus clk signal L_CLKCTLB I O Can be used to contro...

Page 136: ... SDVO DDPB_ 0 P red DDPB_ 1 P green DDPB_ 2 P blue DDPB_ 3 P clock HDMI DVI Port B Data and Clock Lines DDPB_ 0 P TMDSB_DATA2 DDPB_ 1 P TMDSB_DATA1 DDPB_ 2 P TMDSB_DATA0 DDPB_ 3 P TMDSB_CLK DisplayPort Port B DDPB_ 0 P Display Port Lane 0 DDPB_ 1 P Display Port Lane 1 DDPB_ 2 P Display Port Lane 2 DDPB_ 3 P Display Port Lane 3 ...

Page 137: ...B_ 1 N TMDSB_DATA1B DDPB_ 2 N TMDSB_DATA0B DDPB_ 3 N TMDSB_CLKB DisplayPort Port B DDPB_ 0 N Display Port Lane 0 complement DDPB_ 1 N Display Port Lane 1 complement DDPB_ 2 N Display Port Lane 2 complement DDPB_ 3 N Display Port Lane 3 complement DDPB_AUXP I O Port B Display Port Aux DDPB_AUXN I O Port B Display Port Aux Complement DDPB_HPD I Port B TMDSB_HPD Hot Plug Detect SDVO_CTRLC LK I O Port...

Page 138: ...CLKINN Serial Digital Video TVOUT Synchronization Clock Complement SDVO_STALL P I SDVO_STALLP Serial Digital Video Field Stall SDVO_STALL N I SDVO_STALLN Serial Digital Video Field Stall Complement DDPC_ 3 0 P O Port C Capable of HDMI DVI DP HDMI DVI Port C Data and Clock Lines DDPC_ 0 P TMDSC_DATA2 DDPC_ 1 P TMDSC_DATA1 DDPC_ 2 P TMDSC_DATA0 DDPC_ 3 P TMDSC_CLK DisplayPort Port C DDPC_ 0 P Displa...

Page 139: ...DATA1B DDPC_ 2 N TMDSC_DATA0B DDPC_ 3 N TMDSC_CLKB DisplayPort Port C Complements DDPC_ 0 N Lane 0 complement DDPC_ 1 N Lane 1 complement DDPC_ 2 N Lane 2 complement DDPC_ 3 N Lane 3 complement DDPC_AUXP I O Port C Display Port Aux DDPC_AUXN I O Port C Display Port Aux Complement DDPC_HPD I Port C TMDSC_HPD Hot Plug Detect DDPC_CTRLCLK I O HDMI port C Control Clock DDPC_CTRLDAT A I O HDMI port C C...

Page 140: ... Port Lane 3 DDPD_ 3 0 N O Port D Capable of HDMI DVI DisplayPort HDMI DVI Port D Data and Clock Line Complements DDPD_ 0 N TMDSC_DATA2B DDPD_ 1 N TMDSC_DATA1B DDPD_ 2 N TMDSC_DATA0B DDPD_ 3 N TMDSC_CLKB DisplayPort Port D Complements DDPD_ 0 N Lane 0 complement DDPD_ 1 N Lane 1 complement DDPD_ 2 N Lane 2 complement DDPD_ 3 N Lane 3 complement DDPD_AUXP I O Port D Display Port Aux DDPD_AUXN I O P...

Page 141: ...te 12 GPIO74 I O 3 3 V Suspend Native No Multiplexed with SML1ALERT Note 12 GPIO73 I O 3 3 V Suspend Native No Multiplexed with PCIECLKRQ0 GPIO72 I O 3 3 V Suspend Native Mobile Only No Mobile Multiplexed with BATLOW Desktop Unmultiplexed Note 4 GPIO67 I O 3 3 V Core Native No Multiplexed with CLKOUTFLEX3 GPIO66 I O 3 3 V Core Native No Multiplexed with CLKOUTFLEX2 GPIO65 I O 3 3 V Core Native No ...

Page 142: ... Note 12 GPIO51 I O 3 3 V Core Native No Multiplexed with GNT1 GPIO50 I O 5 0 V Core Native No Multiplexed with REQ1 Note 12 GPIO49 I O 3 3V Core GPI No Multiplexed with SATA5GP GPIO48 I O 3 3 V Core GPI No Multiplexed with SDATAOUT1 GPIO47 I O 3 3V Suspend Native No Multiplexed with PEG_A_CLKRQ GPIO46 I O 3 3V Suspend Native No Multiplexed with PCIECLKRQ7 GPIO45 I O 3 3V Suspend Native No Multipl...

Page 143: ...s Multiplexed with SUS_PWR_DN_ACK Desktop Cannot be used for native function Used as GPIO30 only Mobile Used as SUS_PWR_DN_ACK or GPIO30 GPIO29 I O 3 3 V Suspend GPO No Multiplexed with SLP_LAN Note 11 GPIO28 I O 3 3 V Suspend GPI Yes Unmultiplexed GPIO27 I O 3 3 V Suspend GPO Yes Unmultiplexed GPIO26 I O 3 3 V Suspend Native Yes Multiplexed with PCIECLKRQ4 GPIO25 I O 3 3 V Suspend Native Yes Mult...

Page 144: ... OC7 GPIO13 I O 3 3 V Suspend GPI Yes Multiplexed with HDA_DOCK_RST Mobile Only Note 4 GPIO12 I O 3 3 V Suspend GPI Yes Multiplexed with LAN_PHY_PWR_CTRL GPIO Native functionality controlled via soft strap Note 9 GPIO11 I O 3 3 V Suspend Native Yes Multiplexed with SMBALERT Note 12 GPIO10 I O 3 3 V Suspend Native Yes Multiplexed with OC6 Note 12 GPIO9 I O 3 3 V Suspend Native Yes Multiplexed with ...

Page 145: ...l If these GPIOs are outputs there is a danger that a loss of core power PWROK low or a Power Button Override event will result in the Ibex Peak driving a pin to a logic 1 to another device that is powered down 4 The functionality that is multiplexed with the GPIO may not be utilized in desktop configuration 5 When this signal is configured as GPO the output stage is an open drain 6 GPIO18 s blink...

Page 146: ... This pins are used as Functional straps See Section 4 30 for more detail 11 GPIO29 functionality is only enabled in Sx Moff when ME FW has not configured the signal as SLP_LAN GPIO29 must never be used for any purpose other than in association with it muxed native SLP_LAN functionality 12 When the multiplexed GPIO is used as GPIO functionality care should be taken to ensure the signal is stable i...

Page 147: ...atform the signal can be used as a host General Purpose I O or a native function Name Type Description GPIO30 PROC_MISSING Desktop Only I Used to indicate Processor Missing to Ibex Peak Management Engine GPIO24 FP_PWR_EN Mobile Only O Ibex Peak Management Engine drives signal to enable disable power to the Finger Print Sensor device SML0ALERT GPIO60 FP_INT Mobile Only I Used by Finger Print Sensor...

Page 148: ...o indicate AC power source or the system battery Active High indicates AC power Note This signal is required by Management Engine in M3 supporting platforms Signal usage is optional otherwise SUS_PWR_DN_AC K GPIO30 Mobile Only O Active High output signal asserted by the Intel ME to the Embedded Controller when it does not require the PCH Suspend well to be powered Note This signal is required by M...

Page 149: ...ce on core well inputs This power may be shut off in S3 S4 S5 or G3 states V5REF_Sus Reference for 5 V tolerance on suspend well inputs This power is not expected to be shut off unless the system is unplugged VccCore 1 05 V supply for core well logic This power may be shut off in S3 S4 S5 or G3 states Vcc3_3 3 3 V supply for core well I O buffers This power may be shut off in S3 S4 S5 or G3 states...

Page 150: ...ce on core well inputs This power may be shut off in S3 S4 S5 or G3 states V5REF_Sus Reference for 5 V tolerance on suspend well inputs This power is not expected to be shut off unless the system is unplugged VccCore 1 05 V supply for core well logic This power may be shut off in S3 S4 S5 or G3 states Vcc3_3 3 3 V supply for core well I O buffers This power may be shut off in S3 S4 S5 or G3 states...

Page 151: ... battery is removed or completely drained NOTE Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low Clearing CMOS in an Ibex Peak based platform can be done by using a jumper on RTCRST or GPI VccIO 1 05 V supply for core well I O buffers This power may be shut off in S3 S4 S5 or G3 states VccSus3_3 3 3 V supply for suspend well I O buffers This power is not expecte...

Page 152: ...s should be connected to Ground Vcc3_3_NCTF Non Critical To Function These pins are for package mechanical reliability Note These pins should be connected the same as the Vcc3_3 pins VccRTC_NCTF Non Critical To Function These pins are for package mechanical reliability Note These pins should be connected the same as the VccRTC pins VccSUS3_3_N CTF Non Critical To Function These pins are for packag...

Page 153: ...n be left as no connect in On Die VR enabled mode default VccAPLLEXP 1 05 V Analog Power for DMI This power is supplied by the core well This requires an LC filter NOTE This pin can be left as no connect in On Die VR enabled mode default VccFDIPLL 1 05 V analog power supply for the FDI PLL This power is supplied with core well This requires an LC filter NOTE This pin can be left as no connect in O...

Page 154: ...ed the Ibex Peak will read Soft Strap data out of the SPI device prior to the de assertion of reset to both the Management Engine and the Host system Name Usage When Sampled Comment SPKR No Reboot Rising edge of PWROK The signal has a weak internal pull down Note the internal pull down is disabled after PLTRST de asserts If the signal is sampled high this indicates that the system is strapped to t...

Page 155: ...ed the Ibex Peak will read Soft Strap data out of the SPI device prior to the de assertion of reset to both the Management Engine and the Host system Name Usage When Sampled Comment SPKR No Reboot Rising edge of PWROK The signal has a weak internal pull down Note the internal pull down is disabled after PLTRST de asserts If the signal is sampled high this indicates that the system is strapped to t...

Page 156: ... that the system is strapped to the topblock swap mode Ibex Peak inverts A16 for all cycles targeting BIOS space The status of this strap is readable via the Top Swap bit Chipset Config Registers Offset 3414h bit 0 Note that software will not be able to clear the Top Swap bit until the system is rebooted without GNT3 being pulled down INTVRMEN Integrated 1 05 V VRM Enable Disable Always Integrated...

Page 157: ... bit 11 This strap is used in conjunction with Boot BIOS Destination Selection 0 strap Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE If option 00 LPC is selected BIOS may still be placed on LPC but all platforms with Ibex Peak require SPI flash connected directly to the Ibex Peak s SPI bus with a valid descriptor in order to boot NOTE Booting to PCI is intended for d...

Page 158: ... bit 10 This strap is used in conjunction with Boot BIOS Destination Selection 1 strap Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE If option 00 LPC is selected BIOS may still be placed on LPC but all platforms with Ibex Peak require SPI flash connected directly to the Ibex Peak s SPI bus with a valid descriptor in order to boot NOTE Booting to PCI is intended for d...

Page 159: ... bit 10 This strap is used in conjunction with Boot BIOS Destination Selection 1 strap Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC NOTE If option 00 LPC is selected BIOS may still be placed on LPC but all platforms with Ibex Peak require SPI flash connected directly to the Ibex Peak s SPI bus with a valid descriptor in order to boot NOTE Booting to PCI is intended for d...

Page 160: ...sampled high NOTE This strap softstrap AT d_DIS in Section 22 2 5 1 softstrap VE Enabled in Section 22 2 5 11and Ibex Peak SKU capable of AT D are necessary to enable this functionality HDA_DOCK _E N GPIO 33 Flash Descriptor Security Override ME Debug Mode Rising edge of PWROK Signal has a weak internal pull up If strap is sampled high the security measures defined in the Flash Descriptor will be ...

Page 161: ...ulled low GPIO27 On Die PLL Voltage Regulator Rising edge of RSMRST pin This signal has a weak internal pull up Note the internal pull up is disabled after RSMRST de asserts The On Die PLL voltage regulator is enabled when sampled high When sampled low the On Die PLL Voltage Regulator is disabled HDA_SYNC On Die PLL Voltage Regulator Voltage Select Rising edge of RSMRST pin This signal has a weak ...

Page 162: ...IDF U19 APA2031 Headphone U18 APA3010 L speaker R speaker SUBWOOFER U16 KBC IT8502J SATA ODD SATA HDD ESATA USB COBO X10 Receiver U717 CARD READER CONTROLLER 3 in 1slot Fan MMB Button Keyboard Touchpad SPI ROM KBC SATA SATA SATA USB WEBCAM USB USB USB Bluebooth USB USBx3 MINI PCIE WLAN New Card U701 GIGA LAN RTL8111DL RJ45 PCIEx16 DDR3 1066MHZ DMI2 Azalia ...

Page 163: ...6 4 External Monitor No Display 6 5 Memory Failure 6 6 Keyboard K B or Touch Pad T P Failure 6 7 Hard Disk Drive Failure 6 8 ODD Failure 6 9 USB Ports Failure 6 10 Audio Failure 6 11 LAN Failure 6 12 Card Reader Slot Failure 6 13 Mini Express Wireless Socket Failure 6 14 Express Card Socket Failure ...

Page 164: ...chematic in power supply sending out the PG signal If yes we should add the effected analysis into no power chapter 2 No Display Definition Base on the digital IC three basic working conditions working power reset Clock We define the no display as while system leave S5 status but can t get into S0 status Judge condition Check which power will cause no display Check which reset signal will cause no...

Page 165: ...first use AC to power it Check following parts and signals Check following parts and signals Parts Signals No Board level Troubleshooting Replace Motherboard No Power Try another known good battery or AC adapter Is the notebook connected to power either AC adaptor or battery Connect AC adaptor or battery No Replace the faulty AC adaptor or battery Power OK Yes Yes Parts PJ702 PF702 EL709 PR722 PQ7...

Page 166: ...y OK Yes No Correct it Check system clock reset circuit and reference power Replace Motherboard 1 Try another known good CPU module DIMM module 2 Remove all of I O device HDD ODD from motherboard except LCD or monitor Display OK 1 Replace faulty part 2 Connect the I O device to the M B one at a time to find out which part is causing the problem Yes No SMB_CLK SMB_DATA LCD_DDC_CLK LCD_DDC_DATA M96_...

Page 167: ...he I O device cable to the M B one at a time to find out which part is causing the problem Yes No Yes No Re soldering One of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Board level Troubleshooting Replace Motherboard Yes No Graphics Controller Failure LCD No Display Che...

Page 168: ...e M B one at a time to find out which part is causing the problem Yes No Yes No Yes Re soldering No One of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Parts U712 J701 R4 R6 R7 R8 D1 Q1 Q2 U1 U2 EL703 5 Signals 5VS 3VS M96_CRT_DDCK M96_CRT_DDDA M96_CRT_VSYNC M96_CRT_HSYN...

Page 169: ... R774 R795 Signals 1 Check the extend SO DIMM module is installed properly J710 J713 2 Confirm the SO DIMM socket J710 J713 is ok no band pins If your system host bus clock running at 800 MHZ then make sure that SO DIMM module meet require of PC6400 Test OK Yes No M_VREF_DQ_DIMM0 DDR_A B_DQ 0 63 DDR_A B_DQSN 0 7 DDR_A B_DQSP 0 7 DDR_A B_DM 0 7 DDR_CKE 0 3 DDR_A B_BS 0 2 DDR_A B_MA 0 15 DDR_A B_WE ...

Page 170: ...or cold solder Yes No One of the following parts or signals on the motherboard may be defective use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement Yes No Re soldering Parts U16 U712 J3 J4 L44 C321 EL45 EL47 SW2 SW3 Is K B or T P cable connected to notebook properly Yes No Correct it Board level Troubleshooting Replace Motherboard Signals 5VS...

Page 171: ... check the signals or replace the parts one at a time and test after each replacement Yes No Re boot OK Replace the faulty parts 1 Check if BIOS setup is OK 2 Try another working drive Check the system driver for proper installation No Re Test OK End Yes Board level Troubleshooting Replace Motherboard Parts U712 J715 EL738 EL740 R912 C1031 C1032 C1036 C1038 C1018 C1013 C1012 C1025 C1028 Signals 5V...

Page 172: ...nals or replace the parts one at a time and test after each replacement Yes No Test OK Replace the faulty parts 1 Try another known good compact disk 2 Check install for correctly Check the ODD drive for proper installation No Re Test OK Yes Board level Troubleshooting End Replace Motherboard Parts Signals U712 J711 EC766 EC732 EC733 5VS SATA_CDROM_RXP SATA_CDROM_RXN SATA_CDROM_TXN SATA_CDROM_TXP ...

Page 173: ...rts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement No Replace another known good USB device Board level Troubleshooting Correct it Correct it Replace Motherboard Signals Parts U712 J710 J713 BKJ701 EL46 EL64 U7 EL37 U711 EL730 U714 L714 BKEL701 BKEL701 5V SUSC USB_OC2 USB_OC0 USB_OC3 USBPP3 U...

Page 174: ...otherboard may be defective use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement 1 If no sound cause of line out check the following parts signals 2 If no sound cause of MIC check the following parts signals Parts U712 U15 J9 J2 J706 U18 U19 Q38 EL81 R349 R334 Signals AVDD SPDIFOUT PC_BEEP ACZ_RST 0 ACZ_SYNC0 ACZ_SDIN0 ACZ_SDOUT0 AMP_LEFT...

Page 175: ...ective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Parts Signals 1 Check if the driver is installed properly 2 Check if the notebook connect with the LAN properly Yes U712 U701 J703 EL745 EL706 EL707 EL708 R716 R715 C728 C729 PLT_RST PCIE_WAKE LAN_CLKREQ LAN_PCIE_RXN LAN_PCIE_RXP LAN_PCIE_TXP LAN_PCIE_TXN CLK_PCIE_LANP CLK_PC...

Page 176: ...ng parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement U712 U717 J716 R933 R900 ER705 ER706 X705 C1045 C1046 Try another known good card device Correct it Board level Troubleshooting CR_RST SD_DATA2 SD_DATA3 SD_CMD MS_CLK SD_CLK MS_CD SD_D0_MS_D0...

Page 177: ...d device Correct it Replace Motherboard Board level Troubleshooting Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement PCIE_WAKE PEC_CLKREQ_MINI CLK_PCIE_MINI_N CLK_PCIE_MINI_P MINI_PCIE_RXN MINI_PCIE_RXP MINI_PCIE_TXN MINI_P...

Page 178: ...e Correct it Replace Motherboard Board level Troubleshooting Check the following parts for cold solder or one of the following parts on the mother board may be defective use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement Express Card Socket Failure Parts Signals CPUSB USBPN9 USBPP9 SMB_CLK SMB_DATA PCIE_WAKE CPERST CLKREQ_CARD CPPE ...

Page 179: ...D N B Maintenance Reference Material Intel Arrandale Processor Intel INC Intel Ibex Peak chipset Intel INC ATI M96 PRO VGA Controller AMD INC Keyboard controller IT8502J WIN INC Hardware Engineering Specification Technology Corp MITAC ...

Page 180: ... 9270D Sponsoring Editor Miny Feng Author Wenrong Pu Publisher MiTAC Technology Corp Address No 269 Road 2 Export Processing Zone Kunshan P R C Tel 086 512 57367777 Fax 086 512 57385099 First Edition Jan 2010 E mail miny feng mic com tw Web http www mitac com http www mtc mitacservice com ...

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