4.19 JTAG Signals
Name
Type
Description
JTAG_TCK
I/O
Test Clock Input (TCK):
The test clock input provides the
clock for the JTAG test logic.
JTAG_TMS
I/O
Test Mode Select (TMS):
The signal is decoded by the Test
Access Port (TAP) controller to control test operations.
JTAG_TDI
I/O
Test Data Input (TDI):
Serial test instructions and data are
received by the test logic at TDI.
JTAG_TDO
I/O
Test Data Output (TDO):
TDO is the serial output for test
instructions and data from the test logic defined in this
standard.
TRST#
I/O
Test Reset (RST):
RST is an active low asynchronous signal
that can reset the Test Access Port (TAP) controller.
Note:
The RST signal is optional per the IEEE 1149.1
specification, and is not functional for Boundary Scan Testing
NOTE:
JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE Std. 1149.1-2001)
