UPPER LEVEL ASSEMBLY: Theory of Operation
Revision D
APEX Telemetry Transmitter
6-5
401566-166
ECG Circuitry
The ECG circuitry consists of three amplifier stages and a pace stage.
First Amplifier Stage
The first amplifier stage is a unity gain buffer for each of the four patient
lead inputs. Low leakage diodes CR4, CR100, CR103, and CR106 protect
against damage due to defibrillation and static pulses (sheet 1). High-
impedance resistors (R43/R115 and R32/R38) pull up the RA and LL
inputs to +2.5V. LA and V inputs are pulled down to RETURN by high-
impedance resistors (R44/R116 and R118/R127). This causes the first
stage outputs (U4 outputs) to move to +2.5V (RA_BUFFER and
LL_BUFFER) or RETURN (LA_BUFFER and V_BUFFER) to indicate a
lead fail. RL is connected to the +1.25V virtual ground reference.
Analog switches U106 are connected between the RA, LA, and LL input
signals and +1.25V so that the appropriate lead can be connected to the
+1.25V reference during 3 lead operation.
Second Amplifier Stage
The second stage is a differential stage that configures the front end
using crosspoint analog switch U101 (sheet 2). This stage has a gain of
2.5 (U108). The crosspoint switch is controlled by microprocessor U5 and
is configured based on the current lead fail status.
Third Amplifier Stage
The final ECG stage (sheet 4) has slew limiting circuitry of 1.0 V/sec (RTI
- referred to input) (U112, U114), 2.40-Hz high-pass AC coupling filter, a
40-Hz low-pass filter (U110, U115), and a gain of 101. Total ECG gain
through the ECG circuits is 250, so that a maximum input (+/-5mV) is
amplified to the +2.5V A/D converter reference voltage.
Pace Detect
The pace detect circuit processes the DIF1 signal which originates from
the output of the second amplifier of the ECG1 channel, with a third
amplitude limiting amplifier stage (U112) that has a voltage gain of 100.
Amplification of any DC offset voltage by the third stage is eliminated by
a DC offset compensation feedback circuit (U115). The amplified and
amplitude limited input signal is connected to one of the inputs of each of
the two integrated voltage comparators within the pace detect
microcontroller (U116). One of the integrated voltage comparators has its
positive input internally connected to the output of a programmable
reference voltage generator, which is also integrated within the
microcontroller. The other integrated voltage comparator has its
negative input connected to the output of an external reference voltage
inverter amplifier (U108).
