Fujitsu MB89950 Series, Hardware Manual

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CHAPTER 3 CPU
3.6 Clocks
The clock generator provides an internal oscillation circuit. By connecting with external
resonator, the circuits generate the high speed main clock sources. Alternatively,
externally generated clock input can be used.
Clock controller controls the speed and supply of the clock signal according to the
standby mode.
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Clock supply map
Oscillation of a clock and its supply to the CPU and peripheral circuit (peripheral functions) are controlled
by the clock controller. As shown in the map, operating clocks fed to the CPU and peripheral circuits are
affected by standby (sleep/stop) mode.
Divide-by-n output derived from the free-run counter clocked by the peripheral circuit clock is supplied to
the peripheral functions.
Divide-by-n outputs from the timebase timer are also supplied to the peripheral functions.
These clocks, however, are not affected by the speed-shift function, etc. The timebase timer is clocked by
the output of the main clock source oscillator after it is fed through a divide-by-2 circuit.
Figure 3.6-1 "Clock supply map" shows the clock supply map.