Fujitsu MB89950 Series, Hardware Manual

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CHAPTER 7 8-BIT PWM TIMER
Table 7.3-1 PWM control register (CNTR) bits
Bit Function
Bit 7 P/T:
Operating mode
selection bit • This bit switches between the interval timer function (P/T = "0") and PWM timer
function (P/T = "1").
Note:
Write to this bit when the counter operation is stopped (TPE = "0"), interrupts are
disabled (TIE = "0"), and the interrupt request flag bit is cleared (TIR = "0").
Bit 6 Unused bit • The read value is indeterminate.
• Writing to this bit has no effect on the operation.
Bit 5
Bit 4 P1, P0:
Clock selection bits • These bits select the count clock for the interval timer function and PWM timer
function.
• These bits can select the count clock from three internal count clocks or the output
cycle of the PWC timer.
Note:
Do not change P1 and P0 when the counter is operating (TPE = "1").
Bit 3 TPE:
Counter operation
enable bit • This bit activates or stops operation of the PWM timer function and interval timer
function.
• Writing "1" to this bit starts the counter operation. Writing "0" to this bit stops the
count and clears the counter to "00
H
".
Bit 2 TIR:
Interrupt request flag
bit • For the interval timer function:
This bit is set to "1" when the counter and PWM compare register (COMR) value
match.
An interrupt request is issued to the CPU when both this bit and the interrupt request
enable bit (TIE) are "1".
• For the PWM timer function:
Interrupt requests are not generated.
• Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value.
Bit 1 OE:
Output pin control bit • The P41/PWM pin functions as a general-purpose I/O port (P41) when this bit is set to
"0", and a dedicated pin (PWM) when this bit is set to "1".
• The PWM pin outputs a square wave when the interval timer function is selected and a
PWM waveform when the PWM timer function is selected.
Bit 0 TIE:
Interrupt request
enable bit • This bit enables or disables interrupt request output to the CPU. Interrupt request is
generated when both this bit and the interrupt request flag bit (TIR) are "1".