Fujitsu MB89950 Series Hardware Manual Download

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248

CHAPTER 12 LCD CONTROLLER/DRIVER

12.3.3

Display RAM

Display RAM consists of 42 x 4-bit (21 bytes) of display data memory used to generate
the segment output signals.

■

Display RAM and output pins

The contents of display RAM are automatically read out and output via the segment outputs in synchronous

with the selected common signal timing. A "1" bit is converted to a "select" (display on) voltage and a "0"

to a "deselect" (display off) voltage. Since the operation of the LCD is not directly related to the operation

of the CPU, display RAM read/write timing can be set by the user. The SEG20 to SEG41 pins that are not

made dedicated segment outputs by mask option selection may be used as N-ch open-drain I/O port pins,

and the RAM that goes with those pins may be used as regular RAM. (See Table 12.3-3 "Segment outputs,

display RAM locations, and sharing port pins".)

Figure 12.3-7 "Segment/common output pins and corresponding display RAM" shows which display RAM

bits are associated with each segment and common output pin.

Figure 12.3-7 Segment/common output pins and corresponding display RAM

Address

0064

bit3

bit2

bit1

bit0

SEG0

bit7

bit6

bit5

bit4

SEG1

0065

bit3

bit2

bit1

bit0

SEG2

bit7

bit6

bit5

bit4

SEG3

006D

bit3

bit2

bit1

bit0

SEG18

bit7

bit6

bit5

bit4

SEG19

006E

bit3

bit2

bit1

bit0

SEG20

bit7

bit6

bit5

bit4

SEG21

006F

bit3

bit2

bit1

bit0

SEG22

bit7

bit6

bit5

bit4

SEG23

0070

bit3

bit2

bit1

bit0

SEG24

bit7

bit6

bit5

bit4

SEG25

0071

bit3

bit2

bit1

bit0

SEG26

bit7

bit6

bit5

bit4

SEG27

0072

bit3

bit2

bit1

bit0

SEG28

bit7

bit6

bit5

bit4

SEG29

0073

bit3

bit2

bit1

bit0

SEG30

bit7

bit6

bit5

bit4

SEG31

0074

bit3

bit2

bit1

bit0

SEG32

bit7

bit6

bit5

bit4

SEG33

0075

bit3

bit2

bit1

bit0

SEG34

bit7

bit6

bit5

bit4

SEG35

0076

bit3

bit2

bit1

bit0

SEG36

bit7

bit6

bit5

bit4

SEG37

0077

bit3

bit2

bit1

bit0

SEG38

bit7

bit6

bit5

bit4

SEG39

0078

bit3

bit2

bit1

bit0

SEG40

bit7

bit6

bit5

bit4

SEG41

COM3 COM2 COM1 COM0

Pins SEG36 to SEG41 share pins
with Port 2 (P20 to P25).

RAM area and common pins used in 1/2 duty ratio mode

RAM area and common pins used in 1/3 duty ratio mode

RAM area and common pins used in 1/4 duty ratio mode

Pins SEG28 to SEG35 share pins
with Port 1 (P10 to P17).

Pins SEG20 to SEG27 share pins
with Port 0 (P00 to P07).

Summary of Contents for MB89950 Series

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC 8L 8 BIT MICROCONTROLLER MB89950 950A Series HARDWARE MANUAL CM25 10146 1E ...

Page 2: ......

Page 3: ...FUJITSU LIMITED F2MC 8L 8 BIT MICROCONTROLLER MB89950 950A Series HARDWARE MANUAL ...

Page 4: ......

Page 5: ...APTER 1 OVERVIEW This chapter describes the main features and basic specifications of the MB89950 950A series CHAPTER 2 HANDLING DEVICE This chapter describes points to note when using the general purpose single chip microcontroller CHAPTER 3 CPU This chapter describes the functions and operation of the CPU CHAPTER 4 I O PORTS This chapter describes the functions and operation of the I O ports CHA...

Page 6: ...nying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use r...

Page 7: ...mple for description of register name and bit name Notations of a double purpose pin P22 SCK pin Some pins can be used by switching their functions using for example settings by a program Each double purpose pin is represented by separating the name of each function using ...

Page 8: ...s data sheet provides a table of electrical characteristics and vari ous examples of this product F2MC 8L Programming Manual manual including instructions for the F2MC 8L family FR F2MC Family Softune C Compiler Manual required only if C language is used for develop ment manual describing how to develop and activate programs in the C language FR F2MC Family Softune Assembler Manual for V3 manual d...

Page 9: ...field To use a the other development environment contact respective makers References F2MC Development Tool Catalog Microcomputer Product Guide MB89P955 EPROM programmer Programmer available for the MBM27C1001 Package conversion adapter ROM 64QF2 28DP 8L3 MB89PV950 piggyback evaluation device Development tool Main unit Pod Probe MB2141A MB2144 505 MB2144 203 ...

Page 10: ...vi ...

Page 11: ...egisters 33 3 4 Interrupts 35 3 4 1 Interrupt Level Setting Registers ILR1 ILR2 ILR3 36 3 4 2 Interrupt Processing 37 3 4 3 Multiple Interrupts 39 3 4 4 Interrupt Processing Time 40 3 4 5 Stack Operation during Interrupt Processing 41 3 4 6 Stack Area for Interrupt Processing 42 3 5 Resets 43 3 5 1 External Reset Pin 45 3 5 2 Reset Operation 46 3 5 3 Pin States during Reset 48 3 6 Clocks 49 3 6 1 ...

Page 12: ...base Timer Interrupt 106 5 5 Operation of Timebase Timer 107 5 6 Notes on Using Timebase Timer 109 5 7 Program Example for Timebase Timer 110 CHAPTER 6 WATCHDOG TIMER 111 6 1 Overview of Watchdog Timer 112 6 2 Block Diagram of Watchdog Timer 113 6 3 Watchdog Timer Control Register WDTC 115 6 4 Operation of Watchdog Timer 116 6 5 Notes on Using Watchdog Timer 118 6 6 Program Example for Watchdog Ti...

Page 13: ...ERIAL I O 169 9 1 Overview of 8 bit Serial I O 170 9 2 Block Diagram of 8 bit Serial I O 171 9 3 Structure of 8 bit Serial I O 173 9 3 1 Serial Mode Register SMR 176 9 3 2 Serial Data Register SDR 179 9 4 8 bit Serial I O Interrupts 180 9 5 Operation of Serial Output 181 9 6 Operation of Serial Input 183 9 7 States in Each Mode during 8 bit Serial I O Operation 185 9 8 Notes on Using 8 bit Serial ...

Page 14: ...R 246 12 3 3 Display RAM 248 12 4 Operation of LCD Controller Driver 250 12 4 1 Output Waveforms during LCD Controller Driver Operation 1 2 Duty Ratio 251 12 4 2 Output Waveforms during LCD Controller Driver Operation 1 3 Duty Ratio 254 12 4 3 Output Waveforms during LCD Controller Driver Operation 1 4 Duty Ratio 257 12 5 Program Example for LCD Controller Driver 260 APPENDIX 263 APPENDIX A I O Ma...

Page 15: ...d basic specifications of the MB89950 950A series 1 1 MB89950 950A Series Features 1 2 MB89950 950A Series Product Range 1 3 Differences among Products 1 4 Block Diagram of MB89950 950A Series 1 5 Pin Assignment 1 6 Package Dimensions 1 7 I O Pins and Pin Functions ...

Page 16: ...MB89953A MB89P955 only High speed processing at low voltage Minimum execution time 0 8 µs 5 MHz F2MC 8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16 bit arithmetic operations Test and branch instructions Bit manipulation instructions etc Single clock control system Main clock max 5 MHz Four types of timer 21 bit timebase timer Watchdog timer...

Page 17: ...de Stop mode oscillation stops so as to minimize the current consumption Sleep mode CPU stops so as to reduce the current consumption to approx 1 3 of normal I O ports max 33 channels General purpose I O ports N ch open drain 22 Also serve as segment pins General purpose I O ports N ch open drain 4 2 also serve as LCD bias pins General purpose I O ports CMOS 7 6 also serve as peripheral pins ...

Page 18: ... 1 MB89950 950A series product line up Part number MB89951A MB89953A MB89P955 MB89PV950 2 Classification Mask ROM OTP Piggy back ROM size 4K x 8 bits internal mask ROM 8K x 8 bits internal mask ROM 16K x 8 bits internal OTP 32K x 8 bits external ROM RAM size 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits Low power consumption Standby mode Sleep mode and stop mode Process CMOS Operating volta...

Page 19: ...n conversion frequency 204 8 µs 3 36 s Event count function PWC timer 8 bit interval timer operation 8 bit pulse width measurement continuous measurement High width Low width measurement and One cycle measurement Operation clock 0 8 µs 3 2 µs 25 6 µs at 5 MHz UART Transfer data length 5 7 8 bits Internal baud rate generator Max 78125 bps at 5 MHz 8 bit serial I O 8 bits LSB first MSB first selecta...

Page 20: ...is the same For more information about the package see Section 1 6 Package Dimensions For more information about the current consumption see the electrical characteristics in the Data Sheet Mask options Functions that can be selected as options and how to designate these options vary from product to product Before using check Appendix C Mask Options Take particular care on the following points In ...

Page 21: ...circuit Watchdog timer 8 bit PWM timer Port 4 R A M F2MC 8L CPU R O M MODA VCC VSS P41 PWM X0 X1 Internal bus 8 bit pulse width count timer External interrupt P42 PWC INT1 P45 SCK P44 SO P43 SI RST Noise filter 8 bit serial I O UART CMOS I O port N ch open drain I O port 8 P00 SEG20 to P07 SEG27 P10 SEG28 to P17 SEG35 Port 0 1 2 20 SEG0 to SEG19 COM0 to COM3 V3 4 LCD controller driver P40 P46 INT0...

Page 22: ...P12 SEG30 P13 SEG31 P14 SEG32 P15 SEG33 P16 SEG34 P17 SEG35 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 V CC SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 P42 INT1 PWC P43 SI RST P44 SO MODA X0 X1 V SS P45 SCK P46 INT0 P25 SEG41 P24 SEG40 P23 SEG39 P22 SEG38 P21 SEG37 P20 SEG36 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 P33 V2 P32 V1 P31 P30 P40 P41 PWM 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34...

Page 23: ...2 23 24 25 26 27 28 29 30 31 32 RST P44 SO MODA X0 X1 Vss P45 SCK P46 INT0 P25 SEG41 P24 SEG40 P23 SEG39 P22 SEG38 P21 SEG37 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 Vcc SEG13 SEG14 SEG15 SEG16 SEG17 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 94 95 96 65 66 67 68 84 83 82 81 80 79 78 TOP VIEW Pin assignment on package top MB89PV950 only N C Internally...

Page 24: ...width package length 12 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1 70 mm MAX 64 pin plastic LQFP FPT 64P M09 FPT 64P M09 C 2001 FUJITSU LIMITED F64018S c 2 4 0 65 026 0 10 004 1 16 17 32 49 64 33 48 12 00 0 10 472 004 SQ 14 00 0 20 551 008 SQ INDEX 0 32 0 05 013 002 M 0 13 005 0 145 0 055 0057 0022 A 059 008 0 20 1 50 0 25 010 Mounting height 0 50 0 20 020 008 0 60 0 1...

Page 25: ...ITED M64004SC 1 3 15 58 0 20 613 008 16 30 0 33 642 013 18 70 736 TYP INDEX AREA 0 30 012 TYP 1 27 0 13 050 005 22 30 0 33 878 013 24 70 972 TYP 10 16 400 TYP 12 02 473 TYP 14 22 560 TYP 18 12 0 20 713 008 1 27 0 13 050 005 0 30 012 TYP 7 62 300 TYP 9 48 373 TYP 11 68 460 TYP 0 50 020 TYP 0 15 0 05 006 002 10 82 426 MAX 0 40 0 10 016 004 047 016 0 40 1 20 0 40 0 10 016 004 1 00 0 25 039 010 18 00 ...

Page 26: ...this port generates a RESET condition 48 to 41 49 to 42 P00 SEG20 to P07 SEG27 D N channel open drain type general purpose I O ports Also serve as LCD controller driver segment outputs Switching between port output and segment driver output is performed by the mask option 40 to 33 41 to 34 P10 SEG28 to P17 SEG35 D N channel open drain type general purpose I O ports Also serve as LCD controller dri...

Page 27: ...erves as serial I O and UART data output SO A pull up resistor option is provided 25 26 P45 SCK E General purpose I O port Also serves as serial I O and UART clock input output SCK The SCK input is hysteresis type A pull up resistor option is provided 26 27 P46 INT0 E General purpose input port Also serves as external interrupt input INT0 The input is hysteresis type A pull up resistor option is p...

Page 28: ...7 O1 I For data input 78 O2 79 O3 80 VSS O For power supply GND 82 O4 I For data input 83 O5 84 O6 85 O7 86 O8 87 CE O For ROM chip enable The High level is output in standby mode 88 A10 O For address output 89 OE O For ROM output enable The Low level is always output 91 A11 O For address output 92 A9 93 A8 94 A13 O For address output 95 A14 96 VCC O For EPROM power supply 65 N C For internal conn...

Page 29: ...resistor About 1 MΩ 5 V B CMOS input Pull down resistor N ch About 50 kΩ 5 V C Output pull up resistor P ch About 50 kΩ 5 V Hysteresis input D N ch open drain output CMOS input The segment driver output is optional X1 X0 S P ch P ch N ch N ch tandby control signal N ch R R P ch N ch N ch P ch N ch P ch N ch ...

Page 30: ...he pull up resistor is optional About 50 kΩ 5 V F N ch open drain output CMOS input G LCD controller driver common segment driver output H N ch open drain output CMOS input Table 1 7 3 I O circuit type 2 2 Type Circuit Remarks P ch N ch P ch R N ch P ch N ch P ch N ch N ch P ch N ch ...

Page 31: ...17 CHAPTER 2 HANDLING DEVICES This chapter describes points to note when using the general purpose single chip microcontroller 2 1 Notes on Handling Devices ...

Page 32: ...nused input pins open could cause malfunctions They should be connected to pull up or pull down resistor Power supply voltage fluctuations Although VCC power supply voltage is assured to operate within the rated a rapid change to the IC is therefore cause malfunctions even if it occurs within the rated range Stabilizing voltage supplied of the IC is therefore important As stabilization guidelines ...

Page 33: ...nected N C pins open Unused LCD controller driver dedicated pins When LCD controller driver dedicated pins are not in use keep it open Port shared with SEG pin When using port shared with SEG pin be sure that the input voltage to port does not exceed the voltage of V3 SEG driving voltage When power on or reset SEG pin will output an initial value of L LCD controller driver not in use When LCD cont...

Page 34: ...20 CHAPTER 2 HANDLING DEVICES ...

Page 35: ...apter describes the functions and operation of the CPU 3 1 Memory Space 3 2 Dedicated Registers 3 3 General purpose Registers 3 4 Interrupts 3 5 Resets 3 6 Clocks 3 7 Standby Modes Low power Consumption 3 8 Memory Access Mode ...

Page 36: ...ted within the memory space I O can be accessed in the same way as memory High speed access using direct addressing is available RAM area Internal static RAM is provided as an internal data area The internal RAM size differs from product to product Addresses between 0080H and 00FFH support high speed access using direct addressing Addresses between 0100H and 01FFH can be used as the general purpos...

Page 37: ...or table I O RAM ROM MB89P955 0000H 0080H 0100H 0280H FFC0H FFFFH C000H Access prohibited Registers reset interrupt vector call instruction 0200H I O RAM ROM MB89PV950 0000H 0080H 0100H 0480H FFC0H FFFFH 8000H Access prohibited Registers 0200H I O RAM ROM MB89951A 0000H 0080H 0100H FFC0H FFFFH F000H Access prohibited Registers 0140H 00C0H Reserved ...

Page 38: ...rea Can also be used as normal RAM Using the area as general purpose registers enables high speed access by general purpose register addressing using short instructions Table 3 1 1 General purpose register areas lists the areas in each device that can be used for general purpose registers See section 3 2 2 Register Bank Pointer RP and section 3 3 General purpose Registers for details Table 3 1 1 G...

Page 39: ...Section 3 5 Resets and 6 CALLV vct in Appendix B 2 Special Instructions for details Table 3 1 2 Vector table Vector call instruction Vector table address Interrupts Vector table address Upper Lower Upper Lower CALLV 0 FFC0H FFC1H IRQB FFE4H FFE5H CALLV 1 FFC2H FFC3H IRQA FFE6H FFE7H CALLV 2 FFC4H FFC5H IRQ9 FFE8H FFE9H CALLV 3 FFC6H FFC7H IRQ8 FFEAH FFEBH CALLV 4 FFC8H FFC9H IRQ7 FFECH FFEDH CALLV...

Page 40: ...plies to both 16 bit immediate data and operands that specify a memory address Figure 3 1 3 Byte order of 16 bit data in an instruction shows how 16 bit data is stored in an instruction Figure 3 1 3 Byte order of 16 bit data in an instruction Storing 16 bit data on stack The same byte order applies when saving 16 bit register data on the stack during an interrupt or similar The upper byte is store...

Page 41: ...etic operation register The accumulator is used to perform arithmetic operations and data transfers with data in memory or in other registers such as the temporary accumulator T The content of the accumulator can be treated as either word 16 bit or byte 8 bit data Only the lower 8 bits AL of the accumulator are used for byte arithmetic operations or transfers In this case the upper 8 bits AH remai...

Page 42: ...d offset value to the index address generates the memory address for data access The content of the index register after a reset is indeterminate Extra pointer EP The extra pointer is a 16 bit register used to hold a memory address for data access The content of the extra pointer after a reset is indeterminate Stack pointer SP The stack pointer is a 16 bit register used to hold the address referen...

Page 43: ... to 0 otherwise As this flag is for the decimal adjustment instructions do not use this flag in cases other than addition or subtraction Negative flag N Set to 1 if the most significant bit MSB is set to 1 as a result of an arithmetic operation Clear to 0 when the bit is set to 0 Zero flag Z Set to 1 when an arithmetic operation results in 0 Clear to 0 otherwise Overflow flag V Set to 1 if a signe...

Page 44: ...bled when this flag is set to 1 and the CPU accepts interrupt Interrupt is prohibited when this flag is set to 0 and the CPU does not accept interrupt The initial value after a reset is 0 Normal practice is to set the flag to 1 by the SETI instruction and clear to 0 by the CLRI instruction Interrupt level bits IL1 IL0 These bits indicate the level of the interrupt currently being accepted by the C...

Page 45: ...1 CHAPTER 3 CPU Reference The interrupt level bits IL1 IL0 are normally 11B when the CPU is not processing an interrupt during main program execution See Section 3 4 Interrupts for details on interrupts ...

Page 46: ...o the memory block register bank in the RAM area that is used for general purpose registers A total of 32 register banks are available A register bank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bank pointer Each register bank contains eight 8 bit general purpose registers Registers are specified by the lower 3 bits of the operation codes Using the register...

Page 47: ...ks However the number of banks available for general purpose registers is limited on some products if internal RAM only is used The register bank currently in use is specified by the register bank pointer RP The lower three bits of the operation code specify general purpose register 0 R0 to general purpose register 7 R7 Figure 3 3 1 Register bank structure shows the register bank structure Figure ...

Page 48: ...to unintentionally by other routines The interrupt processing routine only needs to specify its dedicated register bank at the start of the routine to effectively save the general purpose registers in use prior to the interrupt Therefore saving the general purpose registers to the stack or other memory location is not necessary This allows high speed interrupt handling while maintaining simplicity...

Page 49: ...n interrupt processing level can be for each interrupt request in the interrupt level setting registers ILR1 ILR2 ILR3 Three levels are available If an interrupt request with the same or lower level occurs during execution of an interrupt processing routine the latter interrupt is not normally processed until the current interrupt processing routine completes If interrupt request set the same leve...

Page 50: ...t level bits in the condition code register CCR IL1 IL0 The CPU does not accept interrupt requests set to interrupt level 3 Table 3 4 2 Interrupt level setting bit and interrupt level shows the relationship between the interrupt level setting bits and the interrupt levels Reference The interrupt level bits in the condition code register CCR IL1 IL0 are normally 11B during main program execution No...

Page 51: ... the interrupt enable flag CCR I Figure 3 4 2 Interrupt processing shows the interrupt processing Figure 3 4 2 Interrupt processing START Initialize peripheral Is an interrupt request present at the peripheral Is interrupt request output enabled for theperipheral Check the interrupt priority level and transfer the level to the CPU Compare the level with the IL bits in PS Is the level higher than I...

Page 52: ...ts in the condition code register CCR IL1 IL0 the CPU checks the interrupt enable flag CCR I and receives the interrupt if interrupts are enabled CCR I 1 6 The CPU saves the contents of the program counter PC and program status PS on the stack reads the top address of the interrupt processing routine from the interrupt vector table for the interrupt updates the interrupt level bits in the conditio...

Page 53: ...upt level bits in the condition code register CCR IL1 IL0 are automatically set to the same value as the interrupt level setting register ILR1 ILR2 ILR3 corresponding to the timer interrupt level 2 in this example If the interrupt request set to higher interrupt level level 1 in this example occurs at this time the interrupt processing has priority To temporarily disable multiple interrupts during...

Page 54: ... Nine instruction cycles are required to perform the following preparation for interrupt processing after the CPU accepts an interrupt request Save the program counter PC and program status PS Set the top address of the interrupt processing routine the interrupt vector in the PC Update the interrupt level bits PS CCR IL1 IL0 in the program status PS Figure 3 4 4 Interrupt processing time shows the...

Page 55: ... execution of the interrupt return instruction RETI at the completion of interrupt processing the CPU performs the opposite processing to interrupt initiation restoring first the program status PS and then the program counter PC from the stack This returns the PS and PC to their states immediately prior to the start of the interrupt Note The CPU does not automatically save the accumulator A or tem...

Page 56: ...s from the bottom RAM address is recommended Figure 3 4 6 Stack area for interrupt processing shows the example of stack area setting Figure 3 4 6 Stack area for interrupt processing Note The stack area is used in the downward direction starting from a high address by functions such as interrupts subroutine calls and the PUSHW instruction Instructions such as return instructions RETI RET and the P...

Page 57: ...t power on reset do not wait for the oscillation stabilization delay time The external reset pin can also function as a reset output pin optional Software reset Writing 0 to the software reset bit in the standby control register STBC RST generates a four instruction cycle reset The software reset does not wait for the oscillation stabilization delay time Watchdog reset The watchdog reset generates...

Page 58: ...t occurs while the device is in main clock mode no stabilization time is provided Table 3 5 2 Reset source and oscillation stabilization delay time shows the relationships between the reset sources and the main clock oscillation stabilization delay time and reset mode mode fetch operations Table 3 5 2 Reset source and oscillation stabilization delay time Reset source Operating state Reset operatio...

Page 59: ...ock diagram of external reset pin External reset pin functions Inputting an L level to the external reset pin RST generates an internal reset signal When selecting products with reset output option setting the pin outputs an L level depending on internal reset sources or during the oscillation stabilization delay time due to an external reset Software reset watchdog reset and power on reset are cl...

Page 60: ...te to RAM the contents of the RAM address cannot be assured Overview of reset operation Figure 3 5 2 Reset operation flow diagram During reset Mode fetch reset operation Normal operation RUN state Software reset Watchdog reset NO NO NO External reset input Power on reset selected YES YES YES Power on Wakes up from external Fetch mode data Fetch reset vector Fetch the instruction code from the addr...

Page 61: ...fter the main clock oscillation stabilization delay time selected by the stabilization delay time option If the CPU has not woken up from the external reset input when the delay time completes the reset operation does not start until the CPU wakes up from external reset As the oscillation stabilization delay time is also required when an external clock is used a reset requires that the external cl...

Page 62: ...ional go to the H level Pin states after reading mode data With a few exceptions the I O pins remain in the high impedance state immediately after reading the mode data pins with a pull up resistor optional go to the H level Note For devices connected to pins that change to high impedance state when a reset source occurs take care that malfunction does not occur due to the change in the pin states...

Page 63: ...functions are controlled by the clock controller As shown in the map operating clocks fed to the CPU and peripheral circuits are affected by standby sleep stop mode Divide by n output derived from the free run counter clocked by the peripheral circuit clock is supplied to the peripheral functions Divide by n outputs from the timebase timer are also supplied to the peripheral functions These clocks...

Page 64: ...Oscillation Watchdog timer 8 bit PWM timer UART Main clock oscillator Divide by two FCH Oscillation stabilization delay controller Pin SCK Free run counter controller Divide by four Sleep stop mode oscillation stabilization delay FCH Main clock oscillation frequency tinst Instruction cycle divide by four main clock oscillation Clock mode Stop mode 3 4 2 8 bit PWC timer 3 3 ...

Page 65: ...al or ceramic resonator Connect as shown in Figure 3 6 2 Connection example for a crystal or ceramic resonator Figure 3 6 2 Connection example for a crystal or ceramic resonator Reference A piezoelectric resonator FAR series that contains the external capacitors can also be used See Data Sheet for details X0 X1 C C Main clock oscillator MB89950 950A series ...

Page 66: ...k Connect the external clock to the X0 pin and leave X1 pin open as shown in Figure 3 6 3 Connection example for external clock Figure 3 6 3 Connection example for external clock X0 X1 Main clock oscillator MB89950 950A series Open ...

Page 67: ... 4 Block diagram of clock controller Main clock oscillator The main clock oscillator is stopped in main stop mode Pin state Stop mode Sleep mode Clock for Main clock oscillator Enable Clock controller Stop of supply to the CPU timebase timer STBC STP SLP SPL RST Divid e by 2 Divide by 4 Clock supply to CPU 1 tinst 214 FCH 218 FCH From timebase timer Oscillation stabiliza tion delay time selector o...

Page 68: ...lation stabilization delay time selector is released Oscillation stabilization delay time selector This selector selects a delay time between two main clock oscillation stabilization times timed by the timebase timer as the duration of CPU clock stop signal STBC register This register controls from normal operation RUN to the standby mode sets the pin states in the stop mode and initiates software...

Page 69: ...quently it is necessary to select an oscillation stabilization delay time that matches the type of oscillator being used Figure 3 6 5 Operation of oscillator after starting oscillation shows the operation of an oscillator after starting oscillation Figure 3 6 5 Operation of oscillator after starting oscillation Main clock oscillation stabilization delay time When first starting operation in main c...

Page 70: ...p conditions vs oscillation stabilization delay time shows the relationships between the conditions in which main clock mode operation is started and oscillation stabilization delay time Table 3 6 1 Main clock startup conditions vs oscillation stabilization delay time Main clock mode startup conditions At power on Exit from stop mode External reset External interrupt Oscillation stabilization dela...

Page 71: ...elationship between standby mode and clock mode and the operation of various sections during standby Standby mode Standby mode reduces the power consumption however by stopping the clock signal supply to the CPU via clock controller sleep mode or by stopping the source oscillator itself stop mode Sleep mode Sleep mode stops the CPU and watchdog timer but operate the peripheral functions Stop mode ...

Page 72: ... in standby mode Table 3 7 1 Operating states of the CPU and peripheral functions in standby mode Function Main clock mode Run Sleep Stop SPL 0 Stop SPL 1 Main clock Operating Operating Stop Stop CPU Instructions Operating Stop Stop Stop ROM Operating Hold Hold Hold RAM Peripheral functions I O ports Operating Hold Hold Hi Z 1 Timebase timer Operating Operating Stop Stop 8 bit PWM timer Operating ...

Page 73: ... to sleep mode even after completion of the interrupt processing Wake up from sleep mode A reset or an interrupt from a peripheral function wakes up the CPU from sleep mode There is no oscillation stabilization delay period The reset operation also initializes the pin states If an interrupt request with an interrupt level higher than 11B occurs from a peripheral function or an external interrupt c...

Page 74: ...peration starts after the main clock oscillation stabilization delay time Products without power on reset do not require for the oscillation stabilization delay time after a reset in stop mode The reset initializes pin states If an interrupt request with an interrupt level higher than 11B occurs from an external interrupt circuit during stop mode the CPU wakes up from stop mode regardless of the i...

Page 75: ...W W R W W RST Software reset bit Read Write 0 Generates a reset signal for four instruction cycles 1 Reading always returns 1 No effect on operation SPL Pin state specification bit 0 External pins hold their states prior to entering stop mode 1 External pins go to high impedance state on entering stop SLP Sleep bit Read Write 0 Reading always returns 0 No effect on operation 1 Goes to sleep mode S...

Page 76: ...ion bit Specifies the states of the external pins during stop mode Writing 0 to this bit specifies that external pins hold their states levels when entering stop mode Writing 1 to this bit specifies that external pins go to high impedance state when entering stop mode pin with a pull up resistor optional go to H level Initialized to 0 by a reset Bit 4 RST Software reset bit Specifies a software re...

Page 77: ...ransition diagram products with power on reset Figure 3 7 3 State transition diagram products without power on reset Power on Oscillation stabilization delay reset state Reset state Power on reset Stop mode RUN state Sleep mode Clock mode Main clock oscillation stabilization delay 1 2 3 3 2 1 8 5 6 7 4 Power on Reset state Stop mode RUN state Sleep mode Clock mode Main clock oscillation stabilizat...

Page 78: ...g reset 3 Have external software or watchdog reset Table 3 7 4 Go to wake up from standby mode State transition Conditions events required for transition Products with power on reset Figure 3 7 2 Products without power on reset Figure 3 7 3 Go to sleep mode 1 STBC SLP 1 1 STBC SLP 1 Wake up from sleep mode 2 Interrupt 3 External reset 2 Interrupt 3 External reset Go to stop mode 4 STBC STP 1 4 STB...

Page 79: ...ral function or others during sleep or stop mode the CPU wakes up from standby mode This does not depend on whether or not the CPU accepts the interrupt After wake up from standby mode the CPU performs the normal interrupt operations If the level set in the interrupt level setting register ILR1 to ILR3 corresponding to the interrupt request is higher than the interrupt level bits in the condition ...

Page 80: ...ation delay time is selected from one of two possible delay times defined by the timebase timer In main clock mode if the interval time set for the timebase timer is less than the oscillation stabilization delay time the timebase timer generates an interval timer interrupt request before the end of the oscillation stabilization delay time To prevent this disable the interrupt request output for th...

Page 81: ...set vector from internal ROM Do not change the mode pin settings even after completion of the reset i e during normal operation Table 3 8 1 Mode pin setting lists the mode pin settings Mode data Always set the mode data in internal ROM to 00H to select single chip mode Figure 3 8 1 Mode data structure Table 3 8 1 Mode pin setting MODA pin state Description VSS Reads the mode data and reset vector ...

Page 82: ...ther modes Prohibited settings Prohibited settings Check mode pin Delay for wake up from external reset or reset source oscillation stabilization delay time Mode fetch Check mode data Set I O pin functions for program execution RUN Reset source generated Mode pin MODA Read mode data from internal ROM I O pins are high impedance Reset active Fetch mode data and reset vector from internal ROM Mode d...

Page 83: ... CHAPTER 4 I O PORTS This chapter describes the functions and operation of the I O ports 4 1 Overview of I O Ports 4 2 Port 0 4 3 Port 1 4 4 Port 2 4 5 Port 3 4 6 Port 4 4 7 Program Example for I O Ports ...

Page 84: ... serves as LCD segment driver pins Port 3 General purpose N ch open drain I O port Also serves as LCD bias pins Port 4 General purpose CMOS I O port Also serves as other peripheral I O pins Table 4 1 1 Port function lists the functions of each port and Table 4 1 2 Port registers lists the registers for each port Table 4 1 1 Port function Port Pin name Input type Output type Function Bit 7 Bit 6 Bi...

Page 85: ...DR0 R W 0000H 11111111B Port 1 data register PDR1 R W 0002H 11111111B Port 2 data register PDR2 R W 0004H 111111B Port 3 data register PDR3 R W 000CH 1111B Port 4 data register PDR4 R W 000EH XXXXXXXB Port 4 data direction register DDR4 W 000FH 0000000B R W Readable and writable W Write only X Indeterminate Unused ...

Page 86: ... used by the peripheral they cannot be used as N ch open drain I O Table 4 2 1 Port 0 pins lists the port 0 pins See Section 1 7 I O Pins and Pin Functions for a description of the circuit type Table 4 2 1 Port 0 pins Port Pin name Function Shared peripheral I O type Circuit type Input Output Port 0 P00 SEG20 P00 N ch open drain I O SEG20 LCD segment driver output CMOS Segment N ch open drain D P0...

Page 87: ...er for port 0 PDR Port data register Internal data bus PDR read for bit manipulation instructions Output latch PDR write Pin N ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 LCD segment driver output Mask option Segment driver output select register Table 4 2 2 Correspondence between pin and register for Port 0 Port Correspondence b...

Page 88: ...gs as an LCD segment driver output To use pins as LCD segment driver outputs segment driver output must be selected by the mask option Furthermore the segment driver output select register must be set to the same as the mask option so that the CMOS input port can be protected Table 4 2 3 Port 0 data register function a lists the functions of the port 0 data register Table 4 2 3 Port 0 data registe...

Page 89: ...gister returns the output latch value Operation as an input port Writing 0 to the PDR0 register set the port as an input port the output transistor is OFF and the pin goes to the high impedance state Reading the PDR0 register returns the pin value Operation as an LCD segment driver output When the LCD output mask option is selected set the PDR0 register bits corresponding to the LCD segment driver...

Page 90: ...n the device goes to stop mode Moreover to avoid leakage from floating input pin input must be driven by either 1 or 0 when SPL 1 Table 4 2 4 Port 0 pin state lists the port 0 pin states Table 4 2 4 Port 0 pin state Pin name Normal operation sleep mode stop mode SPL 0 Stop mode SPL 1 Reset P00 SEG20 to P07 SEG27 General purpose I O ports segment driver output Hi Z Hi Z SPL Pin state specification ...

Page 91: ... used by the peripheral they cannot be used as N ch open drain I O Table 4 3 1 Port 1 pins lists the port 1 pins See Section 1 7 I O Pins and Pin Functions for a description of the circuit type Table 4 3 1 Port 1 pins Port Pin name Function Shared peripheral I O type Circuit type Input Output Port 1 P10 SEG28 P10 N ch open drain I O SEG28 LCD segment driver output CMOS Segment N ch open drain D P1...

Page 92: ...er for port 1 PDR Port data register Internal data bus PDR read for bit manipulation instructions Output latch PDR write Pin N ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 LCD segment driver output Mask option Segment driver output select register Table 4 3 2 Correspondence between pin and register for port 1 Port Correspondence b...

Page 93: ...s as an LCD segment driver output To use pins as LCD segment driver outputs segment driver output must be selected by the mask option Furthermore the segment driver output select register must be set to the same as the mask option so that the CMOS input port can be protected Table 4 3 3 Port 1 data register function lists the functions of the port 1 data register Table 4 3 3 Port 1 data register f...

Page 94: ...egister returns the output latch value Operation as an input port Writing 0 to the PDR1 register set the port as an input port the output transistor is OFF and the pin goes to the high impedance state Reading the PDR1 register returns the pin value Operation as an LCD segment driver output When the LCD output mask option is selected set the PDR1 register bits corresponding to the LCD segment drive...

Page 95: ...n the device goes to stop mode Moreover to avoid leakage from floating input pin input must be driven by either 1 or 0 when SPL 1 Table 4 3 4 Port 1 pin state lists the port 1 pin states Table 4 3 4 Port 1 pin state Pin name Normal operation sleep mode stop mode SPL 0 Stop mode SPL 1 Reset P10 SEG28 to P17 SEG35 General purpose I O ports segment driver output Hi Z Hi Z SPL Pin state specification ...

Page 96: ...t 2 pins Port 2 consists of six N ch open drain I O When pins are used by the peripheral they cannot be used as N ch open drain I O Table 4 4 1 Port 2 pins lists the port 2 pins See Section 1 7 I O Pins and Pin Functions for a description of the circuit type Table 4 4 1 Port 2 pins Port Pin name Function Shared peripheral I O type Circuit type Input Output Port 2 P20 SEG36 P20 N ch open drain I O ...

Page 97: ...gister for port 2 PDR Port data register Internal data bus PDR read for bit manipulation instructions Output latch PDR write Pin N ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 LCD segment driver output Mask option Segment driver output select register Table 4 4 2 Correspondence between pin and register for port 2 Port Corresponden...

Page 98: ...s an LCD segment driver output To use pins as LCD segment driver outputs segment driver output must be selected by the mask option Furthermore the segment driver output select register must be set to the same as the mask option so that the CMOS input port can be protected Table 4 4 3 Port 2 data register function lists the functions of the port 2 data register Table 4 4 3 Port 2 data register func...

Page 99: ...he LCD output mask option is selected set the PDR2 register bits corresponding to the LCD segment driver output pins to 1 to turn the output transistor OFF You cannot read the LCD output data by reading PDR2 Operation at reset Resetting the CPU initializes the PDR2 register values to 1 This turns OFF the output transistor for all pins and all pins are in high impedance Hi Z state Operation in stop...

Page 100: ...pen drain I O pins LCD bias input pins P30 to P33 V2 Port 3 data register PDR3 Port 3 pins Port 3 consists of four N ch open drain I O When pins are used by the peripheral they cannot be used as N ch open drain I O Table 4 5 1 Port 3 pins lists the port 3 pins See Section 1 7 I O Pins and Pin Functions for a description of the circuit type Table 4 5 1 Port 3 pins Port Pin name Function Shared peri...

Page 101: ...lation instructions Output latch PDR write Pin N ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 PDR Port data register Internal data bus PDR read for bit manipulation instructions Output latch PDR write Pin N ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 PSEL bit of ...

Page 102: ...t 3 pin Table 4 5 2 Correspondence between pin and register for port 3 shows the correspondence between the pins and register for port 3 Table 4 5 2 Correspondence between pin and register for port 3 Port Correspondence between register bit and pin Port 3 PDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Corresponding pin P33 P32 P31 P30 ...

Page 103: ...ut V1 and V2 The PSEL bit in the LCD control register must be cleared to 0 in order to select P32 and P33 as LCD controller bias voltage input When LCD bias voltage input is selected by using the PSEL bit in the LCD control register these ports can be used as LCD bias voltage input only Table 4 5 3 Port 3 data register function lists the functions of the port 3 data register Table 4 5 3 Port 3 dat...

Page 104: ... as V1 and V2 When V1 and V2 are selected set the PDR3 register bits corresponding to V1 and V2 pins to 1 to turn the output transistor OFF Operation at reset At reset these ports serve as LCD controller driver bias input Resetting the CPU initializes the PDR3 register values to 1 This turns OFF the output transistor for all pins and all pins are in high impedance Hi Z state Since PSEL bit of LCD ...

Page 105: ...rt 3 pin state Pin name Normal operation sleep mode stop mode SPL 0 Stop mode SPL 1 Reset P30 to P33 V2 General purpose I O ports bias input Hi Z Hi Z SPL Pin state specification bit in the standby control register STBC Hi Z High impedance ...

Page 106: ...ix of these pins are also used as I O pins for various peripherals While they are being used by the peripheral these pins cannot be used as the general purpose I O port Table 4 6 1 Port 4 pins lists the port 4 pins See Section 1 7 I O Pins and Pin Functions for a description of the circuit type Table 4 6 1 Port 4 pins Port Pin name Function Shared peripheral I O type Circuit type Input Output Port...

Page 107: ... read PDR read Output latch PDR write DDR write Pin SPL Pin state specification bit in the standby control register STBC N ch Stop mode SPL 1 To peripheral input Port data direction register Peripheral output Peripheral output enable P ch Pull up resistor Approx 50 k P ch When Read modify write instruction executed Stop mode SPL 1 To external interrupt External interrupt enable Mask option Table 4...

Page 108: ...ion input or output for each pin bit Setting 1 to the bit corresponding to a port pin sets the pin as an output port Setting 0 sets the pin as an input port Settings as a peripheral output To use a peripheral that has an output pin set the peripheral output enable bit for that pin to the enable state As can be seen in the block diagram the peripheral has precedence over the general purpose port fo...

Page 109: ...sistor ON R W 000EH XXXXXXXB 1 Pin state is the H level Sets the pin to the high impedance state if the pin functions as an output port Sets 1 to the output latch and turns the output transistor OFF Port 4 data direction register DDR4 0 Disables the output transistor and sets the pin as an input pin W 000FH 0000000B 1 Enables the output transistor and sets the pin as an output pin R W Readable and...

Page 110: ... latch but does not output the data to the pin Reading the PDR4 register returns the pin value Operation as a peripheral output If a peripheral output enable bit is set to enable the corresponding pin becomes a peripheral output As the pin value can be read even if the peripheral output is enabled the peripheral output value can be read via the PDR4 register Operation as a peripheral input A port ...

Page 111: ...R4 register value Table 4 6 4 Port 4 pin state lists the port 4 pin states Reference Pins with a pull up resistor go to the H level pull up state rather than to the high impedance state when the output transistor is turned OFF Table 4 6 4 Port 4 pin state Pin name Normal operation sleep mode stop mode SPL 0 Stop mode SPL 1 Reset P40 to P46 INT0 General purpose I O port peripheral I O Hi Z Hi Z SPL...

Page 112: ...node common pin of the LED and the P10 to P17 pins operate as the segment pins Figure 4 7 1 Connection example for an eight segment LED shows the connection example for an eight segment LED Figure 4 7 1 Connection example for an eight segment LED Coding example P10 P16 P17 P00 MB89950 950A PDR0 EQU 0000H Address of the port 0 data register DDR0 EQU 0001H Address of the port 0 direction register Ma...

Page 113: ...peration of the timebase timer 5 1 Overview of Timebase Timer 5 2 Block Diagram of Timebase Timer 5 3 Timebase Timer Control Register TBTC 5 4 Timebase Timer Interrupt 5 5 Operation of Timebase Timer 5 6 Notes on Using Timebase Timer 5 7 Program Example for Timebase Timer ...

Page 114: ...g clock for noise filter circuit in PWC timer The timebase timer stops operating in stop mode Interval timer function The interval timer function generates repeated interrupts at fixed time intervals The timer generates an interrupt each time the interval timer bit overflows on the timebase timer counter The interval timer bit interval time can be selected from four different settings Table 5 1 1 ...

Page 115: ...ion cycle is unstable immediately after oscillation starts Table 5 1 2 Clocks supplied by timebase timer Clock destination Clock cycle Remarks Main clock oscillation stabilization delay time 214 FCH approx 3 28 ms Selected by mask option 218 FCH approx 52 43 ms Noise filter circuit in PWC timer 22 FCH approx 0 8 µs Select by noise filter control register 25 FCH approx 6 4 µs 27 FCH approx 25 6 µs ...

Page 116: ...ister TBR 0 the counter is cleared when device goes to stop mode STBC STP 1 or by power on reset optional Interval timer selector Selects one of four operating timebase timer counter bits as the interval timer bit An overflow on the selected bit triggers an interrupt TBTC OF OF OF Timebase timer counter Divide by two FCH Power on reset Stop mode start IRQ6 Timebase timer interrupt OF Overflow Coun...

Page 117: ...103 CHAPTER 5 TIMEBASE TIMER TBTC register The TBTC register is used to select the interval timer bit clear the counter control interrupts and check the state of the timebase timer ...

Page 118: ... TBC0 00000B R W R W W R W R W TBC1 TBC0 Interval time selection bits 0 0 215 FCH 0 1 217 FCH 1 0 219 FCH 1 1 221 FCH TBR Timebase timer initialization bit Read Write 0 Clears timebase timer counter 1 Reading always returns 1 No effect The bit does not change TBIE Interrupt request enable bit 0 Disables interrupt request output 1 Enables interrupt output TBIF Overflow interrupt request flag bit Re...

Page 119: ...t change the bit value Bit 3 TBIE Interrupt request This bit enables or disables an interrupt request output to the CPU An interrupt request is output when both this bit and the overflow interrupt request flag bit TBOF are 1 Bit 2 TBR Timebase timer initialization bit This bit clears the timebase timer counter Writing 0 to this bit clears the counter to 00000H Writing 1 has no effect and does not ...

Page 120: ...IF 0 at the same time References An interrupt request is generated immediately if the TBIF bit is 1 when the TBIE bit is changed from disabled to enabled 0 1 The TBIF bit is not set if the counter is cleared TBTC TBR 0 at the same time as an overflow on the specified bit occurs Oscillation stabilization delay time and timebase timer interrupt If the interval time is set shorter than the main clock...

Page 121: ...lag bit TBIF to 1 when an overflow occurs on the interval timer bit Consequently the timebase timer generates interrupt requests at fixed intervals the selected interval time based on the time that the counter is cleared Operation of clock supply function The timebase timer is also used as a timer to generate the main clock oscillation stabilization delay time The time from when the timebase timer...

Page 122: ...after wake up from stop mode Figure 5 5 2 Operation of timebase timer Counter value 1FFFFFH Oscillationstabilization delay overflow 0000H Power on reset optional CPU operation starts Interval cycle TBTC TBC1 TBC0 11B Cleared by the interrupt processing routine Cleared by going to stop mode Counter clear TBTC TBR 0 TBIF bit TBIE bit SLP bit STBC register STP bit STBC register Sleep mode Wake up fro...

Page 123: ...mer Using as timer for oscillation stabilization delay time As the main clock oscillation frequency is stopped when the power is turned on during stop mode the timebase timer provides the oscillation stabilization delay time after the oscillator starts An appropriate oscillation stabilization delay time must be selected for the type of resonator connected to the main clock oscillator clock generat...

Page 124: ...gister TBIF EQU TBTC 3 Define the interrupt request flag bit ILR2 EQU 007DH Address of the interrupt level setting register 2 INT_V DSEG ABS DATA SEGMENT ORG 0FFEEH IRQ6 DW WARI Set interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts MOV ILR2 11011111B Set interrupt level level 1 MOV TBTC 00010010B Clear interrupt request ...

Page 125: ...functions and operation of the watchdog timer 6 1 Overview of Watchdog Timer 6 2 Block Diagram of Watchdog Timer 6 3 Watchdog Timer Control Register WDTC 6 4 Operation of Watchdog Timer 6 5 Notes on Using Watchdog Timer 6 6 Program Example for Watchdog Timer ...

Page 126: ...n be selected as the watchdog timer count clock Table 6 1 1 Watchdog timer interval time lists the watchdog timer interval times If not cleared the watchdog timer generates a watchdog reset at a time between the minimum and maximum times listed Clear the counter within the minimum time given in the table See Section 6 4 Operation of Watchdog Timer for the details on the minimum and maximum time of...

Page 127: ...er A 2 bit counter that uses the timebase timer output as a count clock Reset controller Generates a reset signal to the CPU when an overflow occurs on the watchdog timer counter Counter clear controller Controls clearing and halting the operation of watchdog timer counter WTE3 WTE2 WTE1 WTE0 WDTC register Counter clear 2 bit counter RST Reset controller controller 221 FCH Timebase timer output Ov...

Page 128: ...6 WATCHDOG TIMER WDTC register The WDTC register is used to select the count clock and to activate or clear the watchdog timer counter As the register is write only the bit manipulation instructions cannot be used ...

Page 129: ...mes after a reset Other than the above No operation Note As the bit 3 0 are write only the bit manipulation instructions for these bits cannot be used W Write only Unused X Indeterminate Table 6 3 1 Watchdog timer control register WDTC bits Bit Function Bit 7 Bit 6 Bit 5 Bit 4 Unused bits The read value is indeterminate Writing to these bits has no effect on operation Bit 3 Bit 2 Bit 1 Bit 0 WTE3 ...

Page 130: ...writing 0101B to the watchdog control bits in the watchdog control register WDTC WTE3 to WTE0 for the second or subsequent times after a reset If the counter is not cleared within the interval time of the watchdog timer the counter overflows and the watchdog timer generates an internal reset signal for four instruction cycles Interval time of watchdog timer The interval time changes depending on w...

Page 131: ...d interval time Minimum time Count clock output of the timebase timer Watchdog clear Overflow 1 bit watchdog counter Watchdog reset Maximum time Watchdog clear Overflow Count clock output of the timebase timer 1 bit watchdog counter Watchdog reset 419 43 ms 838 86 ms ...

Page 132: ...aring watchdog timer Clearing the counter being used as a count clock of the watchdog timer timebase timer or watch prescaler also simultaneously clears the watchdog timer counter The watchdog timer counter is cleared when entering sleep or stop mode Notes on programming When writing a program in which the watchdog timer is repeatedly cleared in the main loop including interrupt processing it shou...

Page 133: ...at 5 MHz operation Coding example WDTC EQU 0009H Address of the watchdog timer control register WDT_CLR EQU 00000101B VECT DSEG ABS DATA SEGMENT ORG 0FFFEH RST_V DW PROG Set reset vector VECT ENDS Main program CSEG CODE SEGMENT PROG Initialization routine after a reset MOVW SP 0280H Set initial value of stack pointer for interrupt processing Initialization of peripheral functions interrupts etc IN...

Page 134: ...120 CHAPTER 6 WATCHDOG TIMER ...

Page 135: ...bit PWM Timer 7 2 Block Diagram of 8 bit PWM Timer 7 3 Structure of 8 bit PWM Timer 7 4 8 bit PWM Timer Interrupts 7 5 Operation of Interval Timer Function 7 6 Operation of PWM Timer Function 7 7 States in Each Mode during 8 bit PWM Timer Operation 7 8 Notes on Using 8 bit PWM Timer 7 9 Program Example for 8 bit PWM Timer ...

Page 136: ... wave output Reference Calculation example for the interval time and square wave frequency In this example the main clock oscillation frequency FCH is 5 MHz the PWM compare register COMR value is set to DDH 221 and the count clock cycle is set to 1 tinst In this case the interval time and the frequency of the square wave output from the PWM pin where the PWM timer operates continuously and the val...

Page 137: ...onverter configuration Figure 7 1 1 Example D A converter configuration using PWM output and low pass filter Reference Interrupt requests are not generated during operation of the PWM function Table 7 1 2 Available PWM wave cycle for PWM timer function 1 2 3 4 Internal count clock 8 bit timer output cycle times Count clock cycle 1 tinst 24 tinst 26 tinst 2 tinst to 29 tinst 23 tinst to 211 tinst 2...

Page 138: ...COMR PWM control register CNTR Block diagram of 8 bit PWM timer Figure 7 2 1 Block diagram of 8 bit PWM timer P T P1 P0 TPE TIR OE TIE Internal data bus COMR PWM compare register IRQ2 Start CLK Clear Over flow 8 bit counter Comparator circuit Count clock selector X 1 X 16 X 64 PWM generator and output controller Output Pin Output pin control bit PWC timer output 1 tinst Timer PWM CNTR 8 8 P41 PWM ...

Page 139: ...ation an interrupt request is generated and if the output pin control bit CNTR OE is 1 the output controller inverts the output level of the PWM pin At the same time the 8 bit counter is cleared When a match is detected during PWM timer operation the PWM generator changes the output level of the PWM pin from H to L The pin is set back to the H level when the next overflow occurs on the 8 bit count...

Page 140: ...Setting the output pin control bit CNTR OE to 1 makes pin P41 PWM the output only pin for 8 bit PWM timer Once this has been done the pin performs its PWM function regardless of the state of the port data register output latch data PDR4 bit 1 Block diagram of 8 bit PWM timer pin Figure 7 3 1 Block diagram of 8 bit PWM timer pin PDR Port data register DDR Internal data bus PDR read PDR read Output ...

Page 141: ...f interrupt request output is enabled CNTR TIE 1 when the counter value matches the value set in the COMR register For PWM function no interrupt request is generated CNTR PWM control register COMR PWM compare register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0012H P T P1 P0 TPE TIR OE TIE 0 000000B R W R W R W R W R W R W R W Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...

Page 142: ...rrupt request output OE Output pin control bit 0 Functions as a general purpose port P41 1 Functions as the interval timer PWM timer output pin PWM TIR Interru pt request flag bit Read Write Interval timer function PWM timer function 0 Counter value and set value do not match No change Clears this bit 1 Counter value and set value match No effect The bit does not change TPE Counter operation enabl...

Page 143: ...ction and interval timer function Writing 1 to this bit starts the counter operation Writing 0 to this bit stops the count and clears the counter to 00H Bit 2 TIR Interrupt request flag bit For the interval timer function This bit is set to 1 when the counter and PWM compare register COMR value match An interrupt request is issued to the CPU when both this bit and the interrupt request enable bit ...

Page 144: ...rom the next cycle after the next match is detected Reference The COMR setting for interval timer operation can be calculated using the following formula COMR register value interval time count clock cycle x instruction cycle 1 PWM timer operation This register is used to set the value to be compared with the counter value The register therefore sets the H width of the pulse The PWM pin outputs an...

Page 145: ...t enable bit is enabled CNTR TIE 1 Write 0 to the TIR bit in the interrupt processing routine to clear the interrupt request The TIR bit is set to 1 when the counter value matches the set value regardless of the value of the TIE bit Reference The TIR bit is not set if the counter is stopped CNTR TPE 0 at the same time as the counter value matches the COMR register value An interrupt request is gen...

Page 146: ... the next rising edge of the count clock clears the counter sets the interrupt request flag bit CNTR TIR 1 and restarts counting from 00H Figure 7 5 2 Operation of 8 bit PWM timer shows the operation of the 8 bit PWM timer Figure 7 5 2 Operation of 8 bit PWM timer CNTR P T P1 P0 TPE TIR OE TIE 0 1 COMR Sets interval time compare value Used bit 1 Set 1 0 Set 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi...

Page 147: ...tion of the interval timer function CNTR TPE 1 References Setting the COMR register value to 00H causes the PWM pin output to be inverted with the cycle of the selected count clock When the counter is stopped CNTR TPE 0 while the interval timer function is selected the PWM pin outputs an L level ...

Page 148: ...re 7 6 2 Example of PWM waveform output PWM pin shows the PWM waveforms output from the PWM pin Figure 7 6 2 Example of PWM waveform output PWM pin Note Do not change the count clock cycle CNTR P1 P0 during operation of the PWM timer function CNTR TPE 1 Reference When the PWM timer function is selected the PWM pin maintains its existing level when the counter is stopped CNTR TPE 0 Bit 7 Bit 6 Bit ...

Page 149: ...ue after wake up from stop mode by an external interrupt Therefore the first interval time or PWM wave cycle does not match the set value Always initialize the 8 bit PWM timer after wake up from stop mode For interval timer function Figure 7 7 1 Counter operation during standby mode or operation halt for interval timer function Counter value COMR value FFH FFH 00H Timer cycle Time TIR bit TPE bit ...

Page 150: ... IRQ2 is not generated Operation halts Maintains the level prior to halting Operation restarts Oscillation stabilization delay time Wake up from stop mode by an external interrupt The PWM pin PWM goes to the high impedance state during stop mode if the pin state specification bit in the standby control register STBC SPL is 1 H level if pull up is selected for PWM pin When the SPL bit is 0 the pin ...

Page 151: ...eration Figure 7 8 1 Error on starting counter operation Notes on setting by program Do not change the count clock cycle CNTR P1 P0 when the interval timer function or PWM timer function is operating CNTR TPE 1 Stop the counter CNTR TPE 0 disable interrupts TIE 0 and clear the interrupt request flag TIR 0 before switching between the interval timer function and PWM timer function CNTR P T Interrup...

Page 152: ...ls Outputs a square wave to the PWM pin that inverts after each interval time With a main clock oscillation frequency FCH of 5 MHz and the highest speed clock selected by the speed shift function 1 instruction cycle time 4 FCH the COMR register is set for an interval time of approximately 5 ms an internal clock period of 64 tinst is selected as the count clock The COMR register setting is calculat...

Page 153: ...DS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB TPE Stop counter operation MOV ILR1 11011111B Set interrupt level level 1 MOV COMR 061H Value compared with the counter value interval time MOV CNTR 00101011B Operate interval timer select 64 tinst start counter operation clear interrupt request flag enable TO pin output enable interrupt req...

Page 154: ...for a duty ratio of 50 COMR register value 50 100 x 256 128 080H Coding example CNTR EQU 0012H Address of the PWM control register COMR EQU 0013H Address of the PWM compare register TPE EQU CNTR 3 Define the counter operation enable bit Main program CSEG CODE SEGMENT CLRB TPE Stop counter operation MOV COMR 80H Set H width of pulse Duty ratio 50 MOV CNTR 10011010B Operate PWM timer select 16 tinst...

Page 155: ...dth Count Timer 8 3 Structure of Pulse Width Count Timer 8 4 Pulse Width Count Timer Interrupts 8 5 Operation of Interval Timer Function 8 6 Operation of Pulse Width Measurement Function 8 7 Operation of Noise Filter Circuit 8 8 States in Each Mode during Pulse Width Count Timer Operation 8 9 Notes on Using Pulse Width Count Timer 8 10 Program Example for Timer Function of Pulse Width Count Timer ...

Page 156: ...ected from three different clocks Two operating modes are available reload timer mode continuous operation and one shot mode one time operation Table 8 1 1 Interval time range lists the available interval time and square wave output ranges The following shows an example of the interval time For a 5 MHz main clock oscillation FCH a PWC reload buffer register RLBR value of DDH 221 and a count clock ...

Page 157: ... different speeds The width of long input pulses can be measured using an interrupt processing routine Table 8 1 2 Available pulse width measured by pulse width measurement function lists the available pulse widths measured by the pulse width measurement function Table 8 1 2 Available pulse width measured by pulse width measurement function Internal count clock cycle Interval time 1 tinst 1 tinst ...

Page 158: ...C pulse width control register 1 PCR1 PWC pulse width control register 2 PCR2 Noise filter control register NCCR Block diagram of pulse width count timer Figure 8 2 1 Block diagram of pulse width count timer FC RM TO C1 C0 W1 W0 Pin PCR1 PCR2 IRQ3 P42 PWC INT1 RLBR X1 X4 X32 EN IE UF IR BF 1 tinst Internal data bus 8 bit down counter Input pulse edge detector Count clock selector To PWM timer Nois...

Page 159: ...se filter circuit The PWC input is sampled by the clock pulse selected by the sample clock selector The sample input signal is integrated to clear the noise Noise filter clock selector Selects a sampling clock for the noise filter circuit from three count clocks of timebase timer RLBR register When operating in reload timer mode of the interval timer function the RLBR register value is re loaded t...

Page 160: ...put to this pin Set the pin as an input port in the port data direction register DDR4 bit 2 0 when using as the PWC pin for the pulse width measurement function Block diagram of pulse width count timer pin Figure 8 3 1 Block diagram of pulse width count timer pin PDR Port data register DDR Internal data bus PDR read PDR read Output latch PDR write DDR write Pin SPL Pin state specification bit in t...

Page 161: ...t value remains in the RLBR register PCR1 PWC pulse width control register 1 PCR2 PWC pulse width control register 2 RLBR PWC reload buffer register NCCR Noise filter control register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0014H EN IE UF IR BF 0 0 000B R W R W R W R W R Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0015H FC RM TO C1 C0 W1 W0 0...

Page 162: ...letion interrupt request flag bit Read Write 0 Pulse width measurement has not completed Clears this bit 1 Pulse width measuremen No effect The bit does not change UF Underflow 01H 00H interrupt request flag bit Read Write 0 No underflow 01H 00H on counter Clears this bit 1 Underflow 01H 00H on counter No effect The bit does not change The UF IR and BF bits are interrupt request flag bits IE Inter...

Page 163: ... request is output when both this bit and the interrupt request enable bit IE are 1 Writing 0 clears this bit Writing 1 has no effect and does not change the bit value Notes When the interval timer function is active the PWC inverts the timer output bit PCR2 TO if the counter underflow 01H 00H occurs In reload timer mode counting down continues from the RLBR register value In one shot timer mode t...

Page 164: ...W R W R W R W R W W1 W0 Measured pulse selection bits Count clock selection bits Reload mode selection bit Operating mode selection bit Timer output bit Only applies to the pulse width measurement function FC 1 0 0 High level 0 1 Low level 1 0 Rising edge to rising edge 1 1 Falling edge to falling edge C1 C0 0 0 1 tinst 0 1 4 tinst 1 0 32 tinst 1 1 Do not use this setting tinst Instruction cycle T...

Page 165: ...unting the number of times this bit is inverted number of underflow 01H 00H occurs pulse widths longer than 28 the cycle of the selected count clock can be measured Bit 4 Unused bit The read value is indeterminate Writing to this bit has no effect on the operation Bit 3 Bit 2 C1 C0 Count clock selection bits These bits select the count clock for the interval timer function and pulse width measurem...

Page 166: ...this register when counter operation is enabled PCR1 EN 1 In reload timer mode the RLBR register value is reloaded to the counter and the counter continues counting down when a counter value underflows 01H 00H If a value is written to the RLBR register during counter operation the new value applies from the next time the counter is reloaded due to an underflow 01H 00H Reference The setting value o...

Page 167: ... measurement completion At this time the buffer full flag bit PCR1 BF and the measurement completion interrupt request flag bit PCR1 IR are set to 1 Reading this register clears the BF bit to 0 The register is read only if the pulse width measurement function is selected Reference The pulse width for the pulse width measurement function is calculated based on the RLBR register value as follows Pul...

Page 168: ...d FCH at 5 MHz Noise pulse width 0 0 No noise filter 0 1 22 FCH 1 0 25 FCH 1 1 27 FCH 25 6 µs 6 4 µs 0 8 µs R W Readable and writable Unused Initial value 128 µs 32 µs 4 0 µs FCH Main clock oscillation frequency Table 8 3 3 PWC noise filter control register NCCR bits Bit Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Unused bits The read value is indeterminate Writing to these bits has no effect on ...

Page 169: ...hen the specified measurement completion edge is detected the measurement completion interrupt request flag bit PCR1 IR and the buffer full flag bit PCR1 BF are set to 1 Also when a counter underflow 01H 00H occurs due to measurement of a long pulse the UF bit is set to 1 At this time an interrupt request IRQ3 to the CPU is generated if the interrupt request enable bit is enabled PCR1 IE 1 Write 0...

Page 170: ...5 1 Interval timer function reload timer mode settings On activation the RLBR register value is loaded to the counter and the counter starts to count down on the rising edge of the selected count clock When the counter value underflows 01H 00H the PWC inverts the timer output bit PCR2 TO value reloads the RLBR register value to the counter and sets the underflow 01H 00H interrupt request flag bit ...

Page 171: ...verts the timer output bit PCR2 TO value automatically clears the counter operation enable bit PCR1 EN 0 to stop counter operation and sets the underflow 01H 00H interrupt request flag bit PCR1 UF 1 on the next rising edge of the count clock Figure 8 5 4 Operation in one shot timer mode shows the operation in one shot timer mode Counter value FFH 80H 00H Timer cycle Cleared by the program Time UF ...

Page 172: ...terval timer function is selected the TO bit maintains the value it had immediately before the counter stopped Counter value FFH 80H 00H Timer cycle Cleared by the program Time UF bit EN bit TOE bit RLBR value FFH TO bit Automatic clear Reactivate Invert Reactivates with the initial value unchanged 0 For an initial value of 1 on activation If the PWC reload buffer register RLBR value is modified d...

Page 173: ...e next rising edge if the input is already H On detection of the measurement completion edge the current down counter value is transferred to the PWC reload buffer register RLBR the measurement completion interrupt request flag bit PCR1 IR and buffer full flag bit PCR1 BF are both set to 1 and counter operation is re enabled The function supports continuous pulse width measurement and so can be us...

Page 174: ...e counter underflows 01H 00H Check the measurement completion interrupt request flag bit PCR1 IR and underflow 01H 00H interrupt request flag bit PCR1 UF in the interrupt processing routine If the UF bit is 1 write 0 to the UF bit to clear the interrupt request and increment the software counter the PWC counter continues to operate When the IR bit is 1 calculate the pulse width including underflow...

Page 175: ... to rising edge Figure 8 6 4 Measuring long pulse width rising edge to rising edge Input pulse Input waveform to the PWC pin EN bit FFH Software counter value Counter value UF bit IR bit BF bit Set 0 One cycle Cleared by the program Cleared by the program Data transferred from down counter to RLBR RLBR read 0 1 2 3 Input pulse EN bit Counter value IR bit BF bit Cleared by the program 0 FFH Input w...

Page 176: ...d to clear the noise By the selecting different value for sampling clock pulse selection bit NCS1 and NCS0 of noise filter control register NCCR different kind of the noise can be filtered out Integrating the sampled signal clears the noise The maximum width of the cleared noise is as follows NW sampling clock cycle x 5 When noise clearing is prohibited the PWC input is input directly to PWC count...

Page 177: ... halts and maintains its current value when the device goes to stop mode Operation starts again from the stored counter value after wake up from stop mode by an external interrupt Therefore the first interval time or pulse width measurement is not correct value Always initialize the pulse width count timer after wake up from stop mode Figure 8 8 1 Counter operation during standby mode or operation...

Page 178: ...n is operating PCR1 EN 1 Stop the counter EN 0 disable interrupts IE 0 and clear the interrupt request flag bits UF IR BF 000B in the PCR1 register before switching between the interval timer function and pulse width measurement function PCR2 FC Interrupt processing cannot return if the interrupt request flag bit PCR1 UF IR or BF is 1 and the interrupt request enable bit is enabled PCR1 IE 1 Alway...

Page 179: ...timer mode Processing description Generates repeated interval timer interrupts at 3 ms intervals reload timer mode The TO bit will be inverted after each interval time cycle The initial value of TO bit is 0 level The following shows the RLBR register value that results in an interval time of approximately 3 ms for a 5 MHz main clock oscillation frequency The count clock is 32 tinst tinst Instructi...

Page 180: ... vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB EN Stop counter operation CLRB IE Disable interrupt request output CLRB BF Clear buffer full flag PCR1 bit 0 MOV ILR1 10111111B Set interrupt level level 2 MOV RLBR 075H Counter reload value interval time MOV PCR2 00001000B Select interval timer function reload timer mode ini...

Page 181: ... interval timer interrupt one shot timer mode The TO bit is initialized to 1 and inverted after the interval time The following shows the RLBR register value that results in an interval time of approximately 3 ms for a 5 MHz main clock oscillation frequency The count clock is 32 tinst tinst Instruction cycle RLBR register value 3 ms 32 x 4 5 MHz 117 2 075H ...

Page 182: ...pt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB EN Stop counter operation CLRB IE Disable interrupt request output CLRB BF Clear buffer full flag PCR1 bit 0 MOV ILR1 0111111B Set interrupt level level 1 MOV RLBR 075H Counter reload value interval time MOV PCR2 01101000B Select interval timer function one shot timer mode ...

Page 183: ...2 Block Diagram of 8 bit Serial I O 9 3 Structure of 8 bit Serial I O 9 4 8 bit Serial I O Interrupts 9 5 Operation of Serial Output 9 6 Operation of Serial Input 9 7 States in Each Mode during 8 bit Serial I O Operation 9 8 Notes on Using 8 bit Serial I O 9 9 Connection Example for 8 bit Serial I O 9 10 Program Example for 8 bit Serial I O ...

Page 184: ...rly the serial I O converts input serial data to parallel and stores the data One shift clock can be selected from one external and three internal clocks The serial I O can control input and output of the shift clock and can output the internal shift clock The data shift direction transfer direction can be selected as either LSB first or MSB first Table 9 1 1 Shift clock cycle and transfer speed S...

Page 185: ...E SIOE SOE SIOF IRQ5 D7 to D0 D7 to D0 D0 to D7 2 P43 SI P44 SO 2tinst 8tinst 32tinst P45 SCK Internal data bus MSB first Transfer direction selection LSB first Pin Pin Pin Shift direction Serial data register SDR Output buffer Output enable Shift clock selection Output enable Output buffer Shift clock controller Overflow Serial mode register SMR Clear Shift clock counter tinst Instruction cycle N...

Page 186: ...unts the number of SDR register shifts generated by the shift clock and overflows after eight shifts The overflow clears the serial I O transfer start bit in the SMR register SST 0 and sets the interrupt request flag SIOF 1 The shift clock counter stops counting when serial transfer halts SST 0 The shift clock counter is cleared when serial transfer restarts SST 1 SDR register The SDR register is ...

Page 187: ...pin as an output pin regardless of the port data direction register DDR4 bit 4 value and sets the pin to function as the SO pin P45 SCK pin The P45 SCK pin can function either as a general purpose I O port P45 or as the shift clock I O for 8 bit serial I O or UART Set P45 SCK pin as an input port in the data direction register DDR4 bit 5 0 when using as SCK pin When using as the shift clock input ...

Page 188: ... bit in the standby control register STBC N ch Stop mode SPL 1 To SIO input Port data direction register SIO output SIO output enable P ch Pull up resistor Approx 50 k P ch When Read modify write instruction executed Stop mode SPL 1 Mask option For P43 SI and P45 SCK P43 SI P44 SO P45 SCK P44 SO P45 SCK SMR Serial mode register SDR Serial data register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B...

Page 189: ...SERIAL I O 8 bit serial I O interrupt source IRQ5 8 bit serial I O generates an interrupt request IRQ5 if interrupt request output is enabled SMR SIOE 1 when the I O function completes input or output of 8 bit serial data ...

Page 190: ...stopped Stops disables serial transfer 1 Serial transfer operating Starts enables serial transfer BDS 0 LSB first starts transfer from the least significant bit 1 MSB first starts transfer from the most significant bit CKS1 CKS0 Shift cl ock sel ecti on bits SCK pin 0 0 Internal shift clock 2 tinst Output 0 1 8 tinst Output 1 0 32 tinst Output 1 1 External shift clock Input tinst Instruction cycle...

Page 191: ... the SCK output pin when shift clock is enabled SCKE 1 regardless of the state of the general purpose I O port P45 Set to shift clock input operation SCKE 0 when using this pin as a general purpose I O port P45 Bit 4 SOE Serial data output enable bit This bit controls serial data output when UART SIO selection bit SMC2 RSEL is set to 1 The P44 SO pin functions as a general purpose I O port P44 whe...

Page 192: ...ng 1 to this bit when an external shift clock is selected CKS1 CKS0 11B enables data transfer clears the shift clock counter and sets serial I O to delay for input of the external shift clock This bit is cleared to 0 and the SIOF bit is set to 1 when transfer completes Writing 0 to this bit while transfer is in progress SST 1 aborts the transfer After halting a transfer data must be set again to t...

Page 193: ... register functions as the transmit data register When serial I O transfer starts SMR SST 1 the 8 bit serial I O performs serial transfer of the data written in the register Serial input operation The register functions as the receive data register When serial I O transfer starts SMR SST 1 the received serial transfer data is stored in this register During serial I O transfer Do not write data to ...

Page 194: ...equest enable bit is enabled SMR SIOE 1 Write 0 to the SIOF bit in the interrupt processing routine to clear the interrupt request The SIOF bit is set after completing 8 bit serial output regardless of the SIOE bit value Reference The interrupt request flag bit is not set SMR SIOF 1 if serial transfer is stopped SMR SST 0 at the same time as serial data transfer completes for the serial I O operat...

Page 195: ...ected internal shift clock At this time the device being communicated with a serial input must be waiting for input of the external shift clock External shift clock Figure 9 5 2 Serial output settings when using external shift clock shows the settings required to operate serial output using an external shift clock Figure 9 5 2 Serial output settings when using external shift clock Enabling serial ...

Page 196: ...put operation Operation at completion of serial output The 8 bit serial I O sets the interrupt request flag bit SMR SIOF 1 and clears the serial I O transfer start bit SMR SST 0 on the rising edge of the shift clock after the serial data of the eighth bit is output 0 1 2 3 4 5 6 7 Bit 7 7 Bit 6 6 Bit 5 5 SDR Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 0 0 1 2 3 4 5 6 7 For LSB first SO pin Serial output...

Page 197: ...he device being communicated with a serial output must have data set in the SDR register and be waiting for input of the external shift clock External shift clock Figure 9 6 2 Serial input settings when using external shift clock shows the settings required to operate serial input using an external shift clock Figure 9 6 2 Serial input settings when using external shift clock Enabling serial input...

Page 198: ...n of serial input The 8 bit serial I O sets the interrupt request flag bit SMR SIOF 1 and clears the serial I O transfer start bit SMR SST 0 on the rising edge of the shift clock after the serial data of the eighth bit is input 0 1 2 3 4 5 6 7 Bit 7 7 Bit 6 6 Bit 5 5 SDR Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 0 7 6 5 4 3 2 1 0 For MSB first SI pin Serial input data Shift clock SIOF bit Interrupt re...

Page 199: ...ialize the 8 bit serial I O depending on the state of the device with the 8 bit serial I O is communicating Figure 9 7 2 Operation in stop mode halt internal shift clock Operation during halt Halting operation during transfer SMR SST 0 halts the transfer and clears the shift clock counter as shown in Figure 9 7 3 Operation during halt internal shift clock Therefore the device being communicated wi...

Page 200: ...alts and transfer aborts as shown in Figure 9 7 5 Operation in stop mode external shift clock Operation restarts after wake up from stop mode This causes an error to occur on the device with which the 8 bit serial I O is communicating Initialize the 8 bit serial I O after wake up from stop mode 0 1 2 3 4 5 0 1 SCK output SST bit SIOF bit SO pin output Operation halts Reset SDR register Operation r...

Page 201: ...he SDR register again before re activating If an external clock is input at this time the SO pin output changes Figure 9 7 6 Operation during halt external shift clock 0 1 2 3 4 5 6 7 Stop request Oscillation stabilization delay time Interrupt request Transfer error occurs Wake up from stop mode by an external interrupt SCK input SST bit SIOF bit SO pin output STP bit Stop mode Clock for next data...

Page 202: ...g an external shift clock and when serial data output is enabled SMR SOE 1 the output level on the SO pin when the external shift clock is the most significant bit when MSB first is selected or least significant bit when LSB first is selected This applies even if serial transfer is stopped SMR SST 0 The interrupt request flag bit SMR SIOF is not set if serial I O transfer is stopped SMR SST 0 at t...

Page 203: ...the SO pin as the serial data output Select an internal shift clock Select the same data transfer shift direction as SIO A Is serial transfer enabled on SIO B 1 Set output data Start serial transfer 2 SST 1 Serial data transfer in progress Have 8 bits been transferred 3 Read input data More data to send Transfer enable state SIO A outputs serial data Simultaneously SIO B inputs serial data Halt op...

Page 204: ...t when transfer is completed The interrupt processing routine resets the transfer data and continues output Operates as an internal shift clock and outputs the shift clock from the SCK pin With a main clock oscillation frequency FCH of 5 MHz the highest speed clock selected by the speed shift function 1 instruction cycle 4 FCH and a 32 tinst shift clock the data transfer rate will be as follows Tr...

Page 205: ...already initialized CLRI Disable interrupts CLRB SST Stop serial I O transfer MOV ILR2 11110111B Set interrupt level level 1 MOV SDR 55H Set transfer data 55H MOV SMR 01111000B Clear Interrupt request flag enable interrupt request output enable shift clock output SCK enable serial data output SO select 32 tinst LSB first SETB SST Start serial I O transfer SETI Enable interrupts Interrupt processin...

Page 206: ...ess of the interrupt level setting register 2 INT_V DSEG ABS DATA SEGMENT ORG 0FFF0H IRQ5 DW WARI Set interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized MOV DDR4 00000000B Set P45 SCK and P43 SI pin as an input CLRI Disable interrupts CLRB SST Stop serial I O transfer MOV ILR2 11110111B Set interrupt level level 1 MOV SMR 01001100B Clear interru...

Page 207: ... describes the functions and operation of the UART 10 1 Overview of UART 10 2 Structure of UART 10 3 UART Pins 10 4 UART Registers 10 5 UART Interrupts 10 6 Operation of UART 10 7 Operation of Mode 0 1 3 10 8 Program Example for UART ...

Page 208: ... transfer mode Internal baud rate generator allows user to select a baud rate from eight different speed for internal clock The baud rate is also configured by setting external clock inputs and 8 bit PWM timer allowing flexible setting of rate The variable data length system allows users to set the data length at 5 8 and 9 bit with non parity or 4 7 and 8 bit with parity See Table 10 1 1 UART oper...

Page 209: ...the input clock of the baud rate generator is selected by PDS1 and PDS0 bits of serial mode control register 2 SMC2 The ratio of dividing frequency is shown in Table 10 1 3 Dividing frequency of dedicated baud rate generator Table 10 1 2 Clock ratio CS1 CS0 Clock input CR Asynchronous Synchronous 0 0 External clock 0 1 16 1 1 1 1 64 0 1 PWM timer 0 1 16 1 2 1 1 64 1 0 Dedicated baud rate generator...

Page 210: ...1 4 Transfer cycle and transfer rate by baud rate generator RC2 RC1 RC0 Division ratio Baud rate bps 4 912 MHz 5 MHz Input clock 1 4 1 4 1 65 PDS division 1 64 1 8 1 16 CS1 CS0 CR division 0 0 0 20 9600 78125 2404 0 0 1 21 4800 39063 1202 0 1 0 22 2400 19531 601 0 1 1 23 1200 9766 300 1 0 0 24 600 4883 150 1 0 1 25 300 2441 75 1 1 0 26 150 1221 38 1 1 1 27 75 610 19 Baud rate value FCH 2 X CPU clo...

Page 211: ...e division value Transfer cycle Transfer rate baud 1 Selected baud rate division value Transfer cycle Transfer rate baud 1 CR 0 16 128 FCH or more 39062 or less 1 8 FCH or more 625k or less CR 1 64 512 FCH or more 9765 or less FCH Main clock oscillation frequency 1 Min external clock cycle of 8 FCH 0 16 µs for FCH set at 5 MHz Baud rate value External clock input FCH 2 4 min CR 0 16 CR 1 64 CR FCH...

Page 212: ...531 3 to 76 3 CR 1 64 610 4 to 2 4 64 tinst CR 0 16 610 4 to 2 4 2 4882 8 to 19 1 CR 1 64 152 6 to 0 6 From PWC timer 1 tinst CR 0 16 19531 3 to 76 3 2 156 3 to 610 4 CR 1 64 4882 8 to 19 1 4 tinst CR 0 16 4882 8 to 19 1 2 39062 to 152 6 CR 1 64 1220 7 to 4 8 32 tinst CR 0 16 610 4 to 2 38 2 4882 8 to 19 1 CR 1 64 152 3 to 0 6 tinst Instruction cycle 1 Main clock oscillation frequency FCH 5 MHz 1 ...

Page 213: ...hift clock Transfer clock Shifter SIDR Parity generator CR RDRF ORFE Transmitter byte count Timing Reset Transmitter control Shift clock Transfer clock Shifter SODR Parity generator TDRE RD8 RP RSEL SOE 2 P44 SO Serial I O data PEN MC1 MC0 PEN TD8 TP MC1 MC0 SBL ORFE RDRF RIE TDRE TIE Internal data bus Registers SMC1 PEN SBL MC1 MC0 SMDE SCKE SOE SMC2 PSEN RSEL PDS1 PDS0 SSD RDRF ORFE TDRE TIE RIE...

Page 214: ...errupt after having received a data of the set length The transmission circuit generates a parity bit when transmitting data with a parity bit When 9 bit long data is sent the MSB of the transmit data is sent Serial mode control register 1 SMC1 This register controls operating modes in the UART The register is used to select parity non parity stop bit length operating mode data length synchronous ...

Page 215: ...utput data register SODR This register stores data to be transmitted The data written in this register is converted to serial data and sent to serial output pin When the data length is set to be 7 bits bit 7 does not have meaning ...

Page 216: ...e the port as a UART clock input pin disable the clock output SMC1 SCKE 0 and configure the port as an input port by setting a corresponding port direction register bit DDR4 bit 5 0 In this case be sure to select an external clock SRC CS1 CS0 00B P44 SO This pin functions either as general purpose input output port P44 or serial data output pin of the UART SO When serial data output is enabled SMC...

Page 217: ... Port data register DDR Internal data bus PDR read PDR read Output latch PDR write DDR write Pin SPL Pin state specification bit in the standby control register STBC N ch Stop mode SPL 1 To peripheral input Port data direction register UART output UART output enable P ch Pull up resistor Approx 50 k P ch When Read modify write instruction executed Stop mode SPL 1 Mask option P45 SCK P44 SO P43 SI ...

Page 218: ... W R W Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0021H CR CS1 CS0 RC2 RC1 RC0 011000B R W R W R W R W R W R W Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0022H RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP 00100 1XB R R R R W R W R W R Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0023H XXXXXXXXB R R R R R R R R Address Bit 7 Bit...

Page 219: ...e bit Operation mode control bit Stop bit length control bit Parity control bit Transfer mode control bits 0 Functions as general purpose I O port P44 Functions as general purpose I O port P45 1 Functions as serial output SO SCKE 0 When the port is set to input DDR4 bit5 0 it also functions as serial clock input pin 1 Functions as serial clock SCK SMDE 0 Synchronous transfer 1 Asynchronous transfe...

Page 220: ...s determine the transfer mode data length Bit 3 SMDE Operation mode control bit This bit selects the UART operating mode In asynchronous mode the UART operates on the serial clock divided by 8 In clock synchronous mode it operates on the selected serial clock Bit 2 Unused bit The read value is indeterminate Writing to this bit has no effect on the operation Bit 1 SCKE Serial clock output bit This ...

Page 221: ...n ratio Baud rate bps 4 9152 MHz 5 MHz Clock 1 4 1 4 1 65 PDS division 1 64 1 8 1 16 CS1 CS0 CR division 0 0 0 20 9600 78125 2404 0 0 1 21 4800 39063 1202 0 1 0 22 2400 19531 601 0 1 1 23 1200 9766 300 1 0 0 24 600 4883 150 1 0 1 25 300 2441 75 1 1 0 26 150 1221 38 1 1 1 27 75 610 19 CS1 CS0 Clock input CR Asynchronous Synchronous 0 0 External clock 0 1 16 1 1 1 1 64 0 1 PWM timer 0 1 16 1 2 1 1 6...

Page 222: ...t are 11B the 1 8 clock rate is selected in spite of the value of the CR bit Bit 4 Bit 3 CS1 CS0 Transfer clock selection bits Used to select the clock input of the UART If the external or internal clock is selected as clock input the baud rate is a 1 16 or 1 64 clock frequency according to the value of the CR bit Bit 2 Bit 1 Bit 0 RC2 RC1 RC0 Baud rate selection bits Used to select the dedicated ...

Page 223: ...ta parity selection bit Transmitted data parity selection bit Receiver interrupt enable bit Transmitter interrupt enable bit Transmission data register empty bit Receive data flag bit Error flag bit 0 Odd parity 1 Even parity TD8 TP 0 Odd parity 1 Even parity RIE 0 Disables interrupt 1 Enables interrupt Enables interrupt TIE 0 Disables interrupt 1 TDRE 0 Full of transmission data 1 Empty RDRF ORFE...

Page 224: ...t This flag represents the status of the serial output data register SODR This flag is cleared when transmission data is written into the SODR register It is set when the data is loaded into the transmit shifter and transmission begins If the TDRE bit is set when the TIE bit is 1 a transmission interrupt request is generated Bit 4 TIE Transmitter interrupt enable bit This bit enables transmission ...

Page 225: ...this register Operation in mode 0 and 1 If received data is normally set in this register the receive data flag bit RDRF is set to 1 and a receive interrupt request occurs if it is enabled When the interrupt request is detected check the RDRF bit in an interrupt processing or in a program If there is receive data stored in this register read this register and then the RDRF flag is cleared automati...

Page 226: ...onverted to serial in the transmit shift register and sent to the serial data output pin SO Writing transmit data to the SODR register sets the transmit data flag to 0 After the transmit data is transferred to the transmit shift register the transmit data flag is set to 1 and the SODR is ready for the next data If transmit interrupt request is enabled interrupt occurs Write next transmission data ...

Page 227: ...l register 2 SMC2 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0024H PSEN RESV RSEL PDS1 PDS0 1 0 00B R W R W R W R W R W PDS1 PDS0 Input clock divider selection bits UART SIO selection bit Baud rate generator enable bit 0 0 Divided by 4 0 1 Divided by 6 1 0 Divided by 13 1 1 Divided by 65 RSEL 0 Function as UART 1 Function as SIO Reserved bit Always write 0 PSEN 0 Stops b...

Page 228: ...d by writing 0 to this bit after transmitting receiving the current serial data then disabled thereafter Bit 4 Reserved bit Always write 0 Bit 3 RSEL UART SIO selection bit The bit is used to select whether the UART or serial I O uses the data and clock I O pins Bit 2 Unused bit The read value is indeterminate Writing to this bit has no effect on the operation Bit 1 Bit 0 PDS1 PDS0 Input clock div...

Page 229: ... pin SO When the UART is ready to accept next data the TDRE is set to 1 and an interrupt request IRQ4 to the CPU is generated if transmit interrupt request is enabled SSD TIE 1 Receive interrupt When the data is received normally stop bit is detected the RDRF is set to 1 When an overrun error a framing error or a parity error occurs their corresponding error flag bit is set to 1 These bits are set...

Page 230: ...to Zero system only The transmission data always begins with a start bit L level followed by a specified length of data bits arranged in the LSB first format and ends with stop bit s H level In asynchronous transfer mode the relation between serial clock and serial input output signal is not as shown in Figure 10 6 1 Transfer data format Figure 10 6 1 Transfer data format shows the relation betwee...

Page 231: ...ta output pin with its LSB Least Significant Bit followed by other bits LSB first When the SODR register gets ready for the next data the TDRE bit is set to 1 and an interrupt request is issued to CPU if interrupt enabled SSD TIE 1 Figure 10 7 2 Transmit operation in mode 0 1 3 shows the transmit operation when mode 1 non parity and 1 stop bit are selected Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 232: ...bits are set when the last stop bit is detected after the completion of the receive operation If the receive interrupt is enabled SSD RIE 1 an interrupt request IRQ 4 is issued to the CPU If the RDRF bit is set the receive data has already been stored to the SIDR register Figure 10 7 3 Receive operation in mode 0 1 3 Figure 10 7 4 Operation at overrun error in mode 0 1 3 and Figure 10 7 5 Operatio...

Page 233: ...eference When the system wakes up from the initialize process caused by reset an initializing period of 11 shift clocks is needed for initializing the internal control blocks Data RDRF Receive interrupt START 0 1 2 3 4 5 6 7 STOP 8 Data ORFE RDRF 1 Receive buffer full Receive interrupt START 0 1 2 3 4 5 6 7 STOP 8 Data ORFE Receive interrupt START 0 1 2 3 4 5 6 7 STOP 8 RDRF 0 ...

Page 234: ...ansmit receive operation using communication functions of the UART P45 SCK P44 SO and P43 SI pins are used for communication Set a transmission speed of 150 baud by the internal baud rate generator A character 13H is transmitted from the SO pin and triggers the operation by interrupt The baud rate is set with the main clock oscillation frequency FCH of 5 MHz ...

Page 235: ...egister INT_V DSEG ABS DATA SEGMENT ORG 0FFF2H IRQ4 DW WARI Set interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT CLRI Disable interrupts MOV ILR2 11111101B Set interrupt level level 1 MOV SMC1 01011011B Non parity 1 stop bit operating mode 1 asynchronous clock output enabled serial data output enabled MOV SRC 00010100B Proprietary baud rate generator selected Set the baud rate at 150 bau...

Page 236: ...222 CHAPTER 10 UART ...

Page 237: ...interrupt circuit 11 1 Overview of the External Interrupt Circuit 11 2 Block Diagram of the External Interrupt Circuit 11 3 Structure of the External Interrupt Circuit 11 4 External Interrupt Circuit Interrupts 11 5 Operation of the External Interrupt Circuit 11 6 Program Example for the External Interrupt Circuit ...

Page 238: ...interrupts can cancel standby mode and return the device to the normal operating state RUN state External interrupt pins 2 pins P42 PWC INT1 and P46 INT0 External interrupt sources Input of a specified edge rising edge or falling edge on the signal input to an external interrupt pin Interrupt control Output of external interrupt requests is enabled or disabled by the interrupt request enable bits ...

Page 239: ...larity of an edge on the input signal to one of the external interrupt pins INT0 INT1 matches the edge polarity specified for the pin in the EIC register SL01 SL00 SL11 SL10 the edge detect circuit sets the corresponding external interrupt request flag bit EIR0 EIR1 to 1 EIC register The EIC register is used for operations such as edge selection enabling or disabling interrupt requests and checkin...

Page 240: ...e Block diagram of the external interrupt circuit pins Figure 11 3 1 Block diagram of the external interrupt circuit pins Table 11 3 1 External interrupt circuit pins External interrupt pin When used as an external interrupt input interrupt requests enabled When used as general I O port interrupt requests disabled P46 INT0 INT0 EIC EIE0 1 P46 EIC EIE0 0 P42 PWC INT1 INT1 EIC EIE1 1 P42 EIC EIE1 0 ...

Page 241: ... interrupt request is generated if an edge of the selected polarity is input to the external interrupt pin INT0 when output of interrupt requests is enabled IRQ1 This interrupt request is generated if an edge of the selected polarity is input to the external interrupt pin INT1 when output of interrupt requests is enabled EIC External interrupt control register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...

Page 242: ...ty selection bits 0 0 No edge detection 0 1 Rising edge 1 0 Falling edge 1 1 Both edge EIR0 INT0 external interrupt request flag bit Read Write 0 The specified edge has not been detected Clears this bit 1 The specified edge has been No effect The bit does not change EIE1 INT1 interrupt request enable bit 0 Disables output of interrupt requests 1 Enables output of interrupt requests SL11 SL10 INT1 ...

Page 243: ...r disables output of interrupt requests to the CPU An interrupt request is generated when both this bit and INT1 external interrupt request flag bit EIR1 are 1 Bit 3 EIR0 INT0 external interrupt request flag bit This bit is set to 1 when the edge selected by INT0 edge polarity selection bits SL01 SL00 is input to external interrupt pin INT0 An interrupt request is output when both this bit and INT...

Page 244: ...t the same time Interrupt processing cannot return if the external interrupt request flag bit is 1 and the interrupt request enable bit is enabled Always clear the external interrupt request flag bit Reference Cancelling stop mode using an interrupt is only possible using the external interrupt circuit An interrupt request is generated immediately if the external interrupt request flag bit is 1 wh...

Page 245: ... interrupt circuit sets the external interrupt request flag bit EIC EIR0 EIR1 to 1 The external interrupt request flag bit is set when the edge polarity match occurs regardless of the value of the interrupt request enable bit EIC EIE0 EIE1 Figure 11 5 2 External interrupt INT1 operation shows the operation when an external interrupt is input to the INT1 pin Figure 11 5 2 External interrupt INT1 op...

Page 246: ...Defines the edge polarity selection bit EIE1 EQU EIC1 4 Defines the interrupt request enable bit ILR1 EQU 007CH Set interrupt level setting register 1 INT_V DSEG ABS DATA SEGMENT ORG 0FFF8H IRQ1 DW WARI Set INT1 interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP etc are already initialized CLRI Disable interrupts CLRB EIR1 Clear interrupt request flag MOV ILR1 11110111B Se...

Page 247: ...e functions and operation of the LCD controller driver 12 1 Overview of LCD Controller Driver 12 2 Block Diagram of LCD Controller Driver 12 3 Structure of LCD Controller Driver 12 4 Operation of LCD Controller Driver 12 5 Program Example for LCD Controller Driver ...

Page 248: ...oltage Can be connected to the external voltage divider Up to 42 segment outputs SEG0 to SEG41 and four common outputs COM0 to COM3 may be used Built in display RAM 21 bytes 42 x 4 bits Three selectable duty ratios 1 2 1 3 and 1 4 Not all duty ratios are available with all bias settings SEG20 to SEG41 can be used as general purpose port option Table 12 1 1 Bias and duty ratio combinations shows th...

Page 249: ... I converter Common output driver Segment output driver Block diagram of LCD controller driver Figure 12 2 1 Block diagram of LCD controller driver LCD control register LCDR This register is used to control the LCD drive supply voltage select display blanking non blanking select the display mode and select the LCD clock cycle Internal bus LCD control register LCDR Prescaler Timing controller Displ...

Page 250: ...er This block controls the segment and common signals based on the frame frequency and LCD control register settings V I converter This circuit generates alternating current waveforms from the voltage signals it receives from the timing controller to drive the LCD Common output driver This block contains the drivers for the LCD common pins Segment output driver This block contains the drivers for ...

Page 251: ...nects the internal voltage divider Set VSEL to 1 when you want to use the internal voltage divider only when no external voltage divider is connected The LCD enable is inactive when LCD operation is stopped LCDR MS1 MS0 00B or in stop mode STBC STP 1 Pin V2 and V1 should be shorted together when using the 1 2 bias setting Figure 12 2 2 Internal voltage divider equivalent circuit shows an equivalen...

Page 252: ...rnal voltage divider is used When internal voltage divider does not provide sufficient LCD display brightness connect an external brightness adjust variable resistor between VCC and V3 as shown in Figure 12 2 4 Use of internal voltage divider with brightness adjustment Figure 12 2 4 Use of internal voltage divider with brightness adjustment V3 R V2 R V1 R V3 V2 V1 N ch V3 R V2 R V1 R V2 V1 N ch LC...

Page 253: ...LCD drive voltage supply pins V1 to V3 Figure 12 2 5 External voltage divider connection shows connection for external voltage divider for the two biasing modes and Table 12 2 1 LCD drive voltages and biasing modes lists the corresponding LCD drive voltages Figure 12 2 5 External voltage divider connection Vcc V3 V2 V1 VR R R VLCD Vcc V3 V2 V1 VR R R VLCD R MB89950 950A series MB89950 950A series ...

Page 254: ... voltage divider from being affected by the internal voltage divider the LCD drive supply voltage control bit of LCD control register LCDR VSEL must be written to 0 to isolate it from the entire internal voltage divider Reference The resistance of RX in the external voltage divider depends on the LCD used Select an appropriate value V3 V2 V1 VR RX RX RX N ch R R R V1 V2 V3 LCD enable MB89950 950A ...

Page 255: ... and P20 SEG36 to P25 SEG41 P00 SEG20 to P07 SEG27 P10 SEG28 to P17 SEG35 and P20 SEG36 to P25 SEG41 pins can function either as N ch open drain I O ports P00 to P07 P10 to P17 and P20 to P25 and LCD segment output pins SEG20 to SEG41 The selection however is made as a mask option Note When these pins are used as LCD segment outputs the corresponding port data registers PDR0 PDR1 and PDR2 should b...

Page 256: ...oltage V3 or V2 LCD drive voltage V1 or Vss Common segment control signal V1 to V3 V1 to V3 pin voltages N ch P ch P ch N ch PDR Port data register Internal data bus PDR read for bit manipulation instructions PDR write Pin N ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 Mask option Output latch Common segment control signal LCD dri...

Page 257: ...ion instructions Output latch PDR write Pin N ch N ch P ch Stop mode SPL 1 SPL Pin state specification bit in the standby control register STBC PDR read Stop mode SPL 1 PSEL bit of LCDR register V1 or V2 P32 V1 P33 V2 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0079H RESV PSEL VSEL BK MS1 MS0 FP1 FP0 0010000B R W R W R W R W R W R W R W R W Address Bit 7 Bit 6 Bit 5 Bit 4...

Page 258: ... supply voltage control bit LCD voltage supply selection bit Reserved bit 0 0 FCH 211 x x x x N 610 Hz 0 1 FCH 212 N 305 Hz 1 0 FCH 213 N 152 Hz 1 1 FCH 214 N 76 Hz Values for FCH 5 MHz and N 4 N Number of time divisions FCH Main clock frequency oscillation MS1 MS0 0 0 Stops LCD operation 0 1 1 2 duty ratio output mode time division N 2 1 0 1 3 duty ratio output mode time division N 3 1 1 1 4 duty...

Page 259: ...is used Bit 4 BK Display blanking selection bit Blanks unblanks the LCD Setting this bit to 1 blank outputs a deselect waveform to the LCD segments which blanks the display Bit 3 Bit 2 MS1 MS0 Display mode selection bits Selects one of three output waveform duty ratio modes The mode selected affects the common pins used Setting both bits to 0 turns off the display stops LCD controller driver displ...

Page 260: ...ent output selection bit Segment output selection bit Segment output selection bit Segment output selection bit Segment output selection bit 0 Select as N ch open drain I O ports P00 to P07 Select as N ch open drain I O ports P10 to P13 Select as N ch open drain I O ports P14 to P15 Select as N ch open drain I O ports P20 to P23 Select as N ch open drain I O ports P24 to P25 Select as N ch open dr...

Page 261: ...sistent with mask option This bit cannot override the mask option Bit 3 SEG12 Segment output selection bit Selects P16 SEG34 to function either as N ch open drain I O port P16 or as LCD segment output SEG34 Note The setting of this bit MUST be consistent with mask option This bit cannot override the mask option Bit 2 SEG11 Segment output selection bit Selects P14 SEG32 to P15 SEG33 to function eit...

Page 262: ... 7 Segment common output pins and corresponding display RAM Address 0064H bit3 bit2 bit1 bit0 SEG0 bit7 bit6 bit5 bit4 SEG1 0065H bit3 bit2 bit1 bit0 SEG2 bit7 bit6 bit5 bit4 SEG3 006DH bit3 bit2 bit1 bit0 SEG18 bit7 bit6 bit5 bit4 SEG19 006EH bit3 bit2 bit1 bit0 SEG20 bit7 bit6 bit5 bit4 SEG21 006FH bit3 bit2 bit1 bit0 SEG22 bit7 bit6 bit5 bit4 SEG23 0070H bit3 bit2 bit1 bit0 SEG24 bit7 bit6 bit5...

Page 263: ...P10 to P17 8 pins SEG0 to SEG31 SEG36 to SEG41 38 pins 64H to 73H 76H to 78H P14 to P17 4 pins SEG0 to SEG39 40 pins 64H to 77H P24 to P25 2 pins SEG0 to SEG33 SEG36 to SEG41 40 pins 64H to 74H 76H to 78H P16 to P17 2 pins SEG0 to SEG34 SEG36 to SEG41 41 pins 64H to 78H P17 1 pin SEG0 to SEG41 42 pins 64H to 78H None Note Locations in the display RAM area that are not required for display data can...

Page 264: ...CDR MS1 MS0 00B and during reset all COM and SEG output pins are pulled L state so that nothing is displayed on the LCD panel Note If the selected frame cycle generate clock were to stop while the LCD is operating the circuit that converts the waveform from d c to a c would also stop causing a d c voltage to be applied to the liquid crystal cells The LCD must therefore be stopped before the clock ...

Page 265: ...not used 1 2 bias 1 2 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment LCD cell is turned on Figure 12 4 2 Output waveforms 1 2 bias and 1 2 duty ratio example shows the output waveforms for the display RAM contents listed in Table 12 4 1 Display RAM contents example Table 12 4 1 Display RAM contents example ...

Page 266: ... V0 Vss V3 ON V2 Vss V2 V3 ON V3 ON V2 Vss V2 V3 ON V3 ON V2 Vss V2 V3 ON V3 ON V2 Vss V2 V3 ON COM0 COM1 COM2 COM3 SEGn SEGn 1 Difference in potential between COM0 and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM0 and SEGn 1 Difference in potential between COM1 and SEGn 1 1 frame 1 cycle V1 to V3 V1 to V3 pin voltages V1 to V3 V1 to V3 pin voltages ...

Page 267: ...M Addre ss Seg men t No 0 to 7 Indicate corresponding display RAM bits Bits 2 3 6 and 7 are not used Address COM3 COM2 COM1 COM0 nH bit3 bit2 bit1 1 bit0 0 SEGn bit7 bit6 bit5 3 bit4 2 SEGn 1 n 1H bit3 bit2 bit1 5 bit0 4 SEGn 2 bit7 bit6 bit5 7 bit4 6 SEGn 3 0 OFF 1 ON Address COM3 COM2 COM1 COM0 064H 1 1 SEG0 1 0 SEG1 065H 1 0 SEG2 0 1 SEG3 LCD Display Bit States for Numerals 0 through 9 bit7 bit...

Page 268: ...eform The maximum potential difference exists between a segment output and the corresponding common output when the segment LCD cell is turned on Figure 12 4 4 Output waveforms 1 3 bias and 1 3 duty ratio example shows the output waveforms for the display RAM contents listed in Table 12 4 2 Display RAM contents example Table 12 4 2 Display RAM contents example Segment Display RAM contents COM3 COM...

Page 269: ...2 V1 VSS V1 V2 V3 ON V3 ON V2 V1 VSS V1 V2 V3 ON V3 ON V2 V1 VSS V1 V2 V3 ON V3 ON V2 V1 VSS V1 V2 V3 ON COM0 COM1 COM2 COM3 SEGn SEGn 1 Difference in potential between COM0 and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM2 and SEGn Difference in potential between COM0 and SEGn 1 Difference in potential between COM1 and SEGn 1 Difference in potential betwe...

Page 270: ...n 2 0 OFF 1 ON Address COM3 COM2 COM1 COM0 064H 0 0 1 SEG0 1 1 1 SEG1 065H 0 1 0 SEG2 0 0 1 SEG3 066H 1 1 1 SEG4 0 1 0 SEG5 Data in unit starting at bit 4 Data in unit starting at bit 0 In 1 3 duty ratio operation to be able to define two digits in three bytes the data stored in two bytes with the first byte starting at bit 0 and second byte starting at bit 4 LCD Display Bit States for Numerals 0 ...

Page 271: ... The maximum potential difference exists between a segment output and the corresponding common output when the segment LCD cell is turned on Figure 12 4 6 Output waveforms 1 3 bias and 1 4 duty ratio example shows the output waveforms for the display RAM contents listed in Table 12 4 3 Display RAM contents example Table 12 4 3 Display RAM contents example Segment Display RAM contents COM3 COM2 COM...

Page 272: ...N V3 ON V2 V1 VSS V1 V2 V3 ON COM0 COM1 COM2 COM3 SEGn SEGn 1 V3 ON V2 V1 VSS V1 V2 V3 ON V3 ON V2 V1 VSS V1 V2 V3 ON Difference in potential between COM0 and SEGn Difference in potential between COM1 and SEGn Difference in potential between COM2 and SEGn Difference in potential between COM3 and SEGn Difference in potential between COM0 and SEGn 1 Difference in potential between COM1 and SEGn 1 Di...

Page 273: ...COM0 COM1 SEGn 1 COM3 LCD Panel Disp lay RAM Addre ss Segment No 0 to 7 Indicate corresponding display RAM bits Address COM3 COM2 COM1 COM0 nH bit3 3 bit2 2 bit1 1 bit0 0 SEGn bit7 7 bit6 6 bit5 5 bit4 4 SEGn 1 0 OFF 1 ON Address COM3 COM2 COM1 COM0 064H 1 1 0 1 SEG0 0 0 1 1 SEG1 LCD Display Bit States for Numerals 0 through 9 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 0 0...

Page 274: ...s writes LCD data to display RAM The data is that required to display the numbers 0 through 9 in an LCD panel connected as shown in Figure 12 4 7 Segment common connections data states and corresponding display The settings are as follows Internal voltage divider is selected LCDR VSEL 1 1 3 bias and 1 4 duty ratio are used The main clock oscillation frequency is 5 MHz The frame frequency is set at...

Page 275: ...11001000B 1 DB 11110110B 2 DB 11111100B 3 DB 11101001B 4 DB 01111101B 5 DB 01111111B 6 DB 11011001B 7 DB 11111111B 8 DB 11111101B 9 DB 00000000B END LCD SEG ENDS Main program CSEG CODE SEGMENT MOVW EP LCRAM Set LCD RAM address MOVW IX LCDDATA Set LCD data table address MOV SEGR 01111111B Set the segment output function LCDSET MOV A IX 00H MOV EP A INCW EP INCW IX BNZ LCDSET Continue until data end...

Page 276: ...262 CHAPTER 12 LCD CONTROLLER DRIVER ...

Page 277: ...s instruction lists and other information APPENDIX A I O Map APPENDIX B Overview of Instructions APPENDIX C Mask Options APPENDIX D Programming Specifications for One Time PROM And EPROM Microcontroller APPENDIX E MB89950 950A Series Pin States ...

Page 278: ...er R W 0001 B 09H WDTC Watchdog timer control register W XXXXB 0AH TBTC Timebase timer control register R W 00000B 0BH Vacancy 0CH PDR3 Port 3 data register R W 1111B 0DH Vacancy 0EH PDR4 Port 4 data register R W XXXXXXXB 0FH DDR4 Port 4 direction register W 0000000B 10H to 11H Vacancy 12H CNTR PWM timer control register R W 0 000000B 13H COMR PWM timer compare register W XXXXXXXXB 14H PCR1 PWC pu...

Page 279: ...R W 00100 1XB 23H SIDR SODR UART serial data register R W XXXXXXXXB 24H SMC2 UART serial mode control register 2 R W 1 0 00B 25H to 2FH Vacancy 30H EIC External interrupt control register R W 00000000B 31H to 63H Vacancy 64H to 78H VRAM LCD data RAM R W XXXXXXXXB 79H LCDR LCD control register R W 0010000B 7AH SEGR Segment output select register R W 0000000B 7BH Vacancy 7CH ILR1 Interrupt level set...

Page 280: ...Instructions Appendix B describes the instructions used by the F2MC 8L B 1 Overview of F2MC 8L Instructions B 2 Addressing B 3 Special Instructions B 4 Bit Manipulation Instructions SETB CLRB B 5 F2 MC 8L Instructions B 6 Instruction Map ...

Page 281: ...s and the instruction map Figure B 1 1 Relationship between the instruction codes and the instruction map The instructions are classified into four types transfer arithmetic branch and other A variety of addressing methods is available One of ten addressing modes can be selected depending on the selected instruction and specified operand s Bit manipulation instructions are provided They can be use...

Page 282: ...f the accumulator 8 bits T Temporary accumulator 8 or 16 bits which are determined depending on the instruction being used TH Higher 8 bits of the temporary accumulator 8 bits TL Lower 8 bits of the temporary accumulator 8 bits IX Index register 16 bits EP Extra pointer 16 bits PC Program counter 16 bits SP Stack pointer 16 bits PS Program status 16 bits dr Either accumulator or index register 16 ...

Page 283: ...and 00FFH In this addressing mode the higher byte of the address is 00H and the lower byte is specified by the operand Figure B 2 1 Example of direct addressing shows an example Figure B 2 1 Example of direct addressing Extended addressing Extended addressing is indicated by ext in the instruction list This addressing is used to access the entire 64 KB area In this addressing mode the first operan...

Page 284: ...addressing is used to access the entire 64 KB area In this addressing mode the address is the value resulting from sign extending the contents of the first operand and adding them to IX index register Figure B 2 4 Example of index addressing shows an example Figure B 2 4 Example of index addressing Pointer addressing Pointer addressing is indicated by EP in the instruction list This addressing is ...

Page 285: ...ts of the operation code Figure B 2 6 Example of general purpose register addressing shows an example Figure B 2 6 Example of general purpose register addressing Immediate addressing Immediate addressing is indicated by d8 in the instruction list This addressing is used when immediate data is required In this addressing mode the operand is used as immediate data Whether the data is specified in by...

Page 286: ...sses are created as shown in Table B 2 1 Vector table addresses corresponding to vct Figure B 2 8 Example of vector addressing shows an example Figure B 2 8 Example of vector addressing Table B 2 1 Vector table addresses corresponding to vct vct Vector table address higher address lower address of branch destination 0 FFC0H FFC1H 1 FFC2H FFC3H 2 FFC4H FFC5H 3 FFC6H FFC7H 4 FFC8H FFC9H 5 FFCAH FFCB...

Page 287: ...shows an example Figure B 2 9 Example of relative addressing In this example a branch to the address of the BNE operation code occurs thus resulting in an infinite loop Inherent addressing Inherent addressing is indicated as the addressing without operands in the instruction list This addressing is used to perform the operation determined by the operation code In this addressing mode different ope...

Page 288: ...en the instruction is executed in the main routine so that a specific subroutine is called whether A contains a predetermined value can be checked by the subroutine This can be used to determine that the branch source is not any unexpected section of the program and to check for program runaway Figure B 3 2 MOVW A PC shows a summary of the instruction Figure B 3 2 MOVW A PC After the MOVW A PC ins...

Page 289: ...nsigned 8 bit value in AL and stores the 8 bit result and the 8 bit remainder in AL and TL respectively A value of 0 is set to both AH and TH The contents of AH before execution of the instruction are not used for the operation An unpredictable result is produced from data that results in more than eight bits In addition there is no indication of the result having more than eight bits Therefore if...

Page 290: ...ed A contains the address of the operation code of the next instruction rather than the address of the operation code of XCHW A PC Accordingly Figure B 3 5 XCHW A PC shows that A contains 1235H which is the address of the operation code of the instruction that follows XCHW A PC This is why 1235H is stored instead of 1234H Figure B 3 6 Example of using XCHW A PC shows an assembly language example F...

Page 291: ...ng CALLV 3 shows a summary of the instruction Figure B 3 7 Example of executing CALLV 3 After the CALLV vct instruction is executed the contents of PC saved on the stack area are the address of the operation code of the next instruction rather than the address of the operation code of CALLV vct Accordingly Figure B 3 7 Example of executing CALLV 3 shows that the value saved in the stack 1232H and ...

Page 292: ... read differs between a normal read operation and a read modify write operation I O ports during a bit manipulation From some I O ports an I O pin value is read during a normal read operation while an output latch value is read during a bit manipulation This prevents the other output latch bits from being changed accidentally regardless of the I O directions and states of the pins Interrupt reques...

Page 293: ... 1 Ri A 48 to 4F 6 MOV A d8 2 2 A d8 AL 04 7 MOV A dir 3 2 A dir AL 05 8 MOV A IX off 4 2 A IX off AL 06 9 MOV A ext 4 3 A ext AL 60 10 MOV A A 3 1 A A AL 92 11 MOV A EP 3 1 A EP AL 07 12 MOV A Ri 3 1 A Ri AL 08 to 0F 13 MOV dir d8 4 3 dir d8 85 14 MOV IX off d8 5 3 IX off d8 86 15 MOV EP d8 4 2 EP d8 87 16 MOV Ri d8 4 2 Ri d8 88 to 8F 17 MOVW dir A 4 2 dir AH dir 1 AL D5 18 MOVW IX off A 5 2 IX o...

Page 294: ...EP d16 E7 30 MOVW IX A 2 1 IX A E2 31 MOVW A IX 2 1 A IX dH F2 32 MOVW SP A 2 1 SP A E1 33 MOVW A SP 2 1 A SP dH F1 34 MOV A T 3 1 A T 82 35 MOVW A T 4 1 A TH A 1 TL 83 36 MOVW IX d16 3 3 IX d16 E6 37 MOVW A PS 2 1 A PS dH 70 38 MOVW PS A 2 1 PS A 71 39 MOVW SP d16 3 3 SP d16 E5 40 SWAP 2 1 AH AL AL 10 41 SETB dir b 4 2 dir b 1 A8 to AF 42 CLRB dir b 4 2 dir b 0 A0 to A7 43 XCH A T 2 1 AL TL AL 42...

Page 295: ...Ri C 38 to 3F 9 SUBC A d8 2 2 A A d8 C 34 10 SUBC A dir 3 2 A A dir C 35 11 SUBC A IX off 4 2 A A IX off C 36 12 SUBC A EP 3 1 A A EP C 37 13 SUBCW A 3 1 A T A C dH 33 14 SUBC A 2 1 AL TL AL C 32 15 INC Ri 4 1 Ri Ri 1 C8 to CF 16 INCW EP 3 1 EP EP 1 C3 17 INCW IX 3 1 IX IX 1 C2 18 INCW A 3 1 A A 1 dH C0 19 DEC Ri 4 1 Ri Ri 1 D8 to DF 20 DECW EP 3 1 EP EP 1 D3 21 DECW IX 3 1 IX IX 1 D2 22 DECW A 3 ...

Page 296: ... 2 2 A AL d8 R 54 41 XOR A dir 3 2 A AL dir R 55 42 XOR A EP 3 1 A AL EP R 57 43 XOR A IX off 4 2 A AL IX off R 56 44 XOR A Ri 3 1 A AL Ri R 58 to 5F 45 AND A 2 1 A AL TL R 62 46 AND A d8 2 2 A AL d8 R 64 47 AND A dir 3 2 A AL dir R 65 48 AND A EP 3 1 A AL EP R 67 49 AND A IX off 4 2 A AL IX off R 66 50 AND A Ri 3 1 A AL Ri R 68 to 6F 51 OR A 2 1 A AL TL R 72 52 OR A d8 2 2 A AL d8 R 74 53 OR A di...

Page 297: ...6 OR A Ri 3 1 A AL Ri R 78 to 7F 57 CMP dir d8 5 3 dir d8 95 58 CMP EP d8 4 2 EP d8 97 59 CMP IX off d8 5 3 IX off d8 96 60 CMP Ri d8 4 2 Ri d8 98 to 9F 61 INCW SP 3 1 SP SP 1 C1 62 DECW SP 3 1 SP SP 1 D1 Table B 5 2 Arithmetic operation instructions Continued No MNEMONIC Operation TL TH AH N Z V C OP CODE ...

Page 298: ... 2 if N 1 then PC PC rel FB 6 BP rel 3 2 if N 0 then PC PC rel FA 7 BLT rel 3 2 if V N 1 then PC PC rel FF 8 BGE rel 3 2 if V N 0 then PC PC rel FE 9 BBC dir b rel 5 3 if dir b 0 then PC PC rel B0 to B7 10 BBS dir b rel 5 3 if dir b 1 then PC PC rel B8 to BF 11 JMP A 2 1 PC A E0 12 JMP ext 3 3 PC ext 21 13 CALLV vct 6 1 vector call E8 to EF 14 CALL ext 6 3 subroutine call 31 15 XCHW A PC 3 1 PC A ...

Page 299: ... Other instructions Table B 5 4 Other instructions No MNEMONIC Operation TL TH AH N Z V C OP CODE 1 PUSHW A 4 1 40 2 POPW A 4 1 dH 50 3 PUSHW IX 4 1 41 4 POPW IX 4 1 51 5 NOP 1 1 00 6 CLRC 1 1 R 81 7 SETC 1 1 S 91 8 CLRI 1 1 80 9 SETI 1 1 90 ...

Page 300: ...PS MOVW PS A OR A ORW A OR A d8 OR A dir OR A IX d OR A EP OR A R0 OR A R1 OR A R2 OR A R3 OR A R4 OR A R5 OR A R6 OR A R7 CLRI CLRC MOV A T MOVW A T DAA MOV dir d8 MOV IX d d8 MOV EP d8 MOV R0 d8 MOV R1 d8 MOV R2 d8 MOV R3 d8 MOV R4 d8 MOV R5 d8 MOV R6 d8 MOV R7 d8 SETI SETC MOV A A MOVW A A DAS CMP dir d8 CMP IX d d8 CMP EP d8 CMP R0 d8 CMP R1 d8 CMP R2 d8 CMP R3 d8 CMP R4 d8 CMP R5 d8 CMP R6 d8...

Page 301: ...d Power on reset available 4 Selection of main clock oscillation stabilization time at 5 MHz 1 About 218 FCH about 52 4 ms About 214 FCH about 3 28 ms Can be selected Can be selected 218 FCH 5 Reset pin output Reset output available Reset output unavailable Can be selected Can be selected Reset output available FCH main clock oscillation frequency 1 The main clock oscillation stabilization time is...

Page 302: ...13 X X X O O X X 38 15 X X O O O X X 34 19 X O O O O X X 26 27 O O O O O X X 40 13 X X X X X X O 22 31 O O O O O O X 20 33 O O O O O O O X Mask option is selected for LCD segment outputs O Mask option is selected for port outputs 1 This column of numbers assume that all the multiplexed peripherals are disabled If any customer wants to choose the mask option combination which is not shown in Table ...

Page 303: ...tions for One Time PROM And EPROM Microcontroller This appendix describes the programming specifications for one time PROM and EPROM microcontroller D 1 Programming Specifications for One time PROM and EPROM Microcontrollers D 2 Programming Yield and Erasure D 3 Programming to the EPROM with Piggyback Evaluation Device ...

Page 304: ...mer inserting a capacitor of about 0 1 µF between VPP and VSS or VCC and VSS can stabilize programming operations Table D 1 1 EPROM programmer socket adaptor lists the EPROM programmer socket adaptors Memory map in EPROM mode Table D 1 1 Memory map in EPROM mode shows the memory map in EPROM mode Write the option data in the option setting area after consulting the OTPROM option bit map Figure D 1...

Page 305: ... Figure D 1 2 Screening procedure Programming to the EPROM In EPROM mode the MB89P955 function is equivalent to the MBM27C256A Programming procedure 1 Set the EPROM programmer to the MBM27C256A 2 Load program data from 4000H to 7FFFH of the EPROM writer Note that 0C000H to 0FFFFH in the operation mode are equivalent to 4000H to 7FFFH in the EPROM mode Load option data from 3FF0H to 3FF6H of the EP...

Page 306: ...eadable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable 3FF3H Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable Vacant Readable Writable 3FF4H Vacant Readable Writable Vacant Readable Writable Vacant Readable Writa...

Page 307: ...seconds cm2 is required to completely erase an internal EPROM This dosage can be obtained by exposure to an ultraviolet lamp wavelength of 2537 Angstroms with intensity of 12000 µW cm2 for 15 to 21 minutes The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure It is important to note that the internal EPROM and simila...

Page 308: ... Memory space Figure D 3 1 Memory map of piggyback evaluation device Programming to EPROM 1 Set the EPROM programmer to the MBM27C256A 2 Load program data into the EPROM programmer at 0000H to 7FFFH 3 Program to 0000H to 7FFFH with the EPROM programmer Table D 3 1 Programming socket adaptor Package Adaptor socket part number LCC 32 Rectangle ROM 32LC 28DP YG Inquiries Sun Hayato Co Ltd Phone 81 3 ...

Page 309: ...ipheral output Port I O Peripheral output Low High impedance 1 Peripheral output Low High impedance 1 X0 Input for oscillation Input for oscillation High impedance 1 High impedance 1 Input for oscillation X1 Output for oscillation Output for oscillation High output High output Output for oscillation MODA Mode input Mode input Mode input Mode input Mode input RST Reset input Reset input Reset input...

Page 310: ...296 APPENDIX ...

Page 311: ...297 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...

Page 312: ... differences among products 6 display brightness adjustment when internal voltage divider is used 238 display RAM and output pin 248 E effect of reset on RAM content 47 EPROM for use 294 EPROM microcomputer note on using and data erasure on 293 EPROM mode memory map in 290 EPROM programmer socket adaptor 290 EPROM programming to 291 294 external interrupt circuit interrupt source 227 external inte...

Page 313: ...rogram example for 260 LCD driving waveform 250 M main clock oscillation stabilization delay time 55 main clock oscillation stabilization delay time and reset source 44 mask option 287 MB89950 950A series block diagram 7 MB89950 950A series pin state 295 measuring long pulse widths 160 memory access mode selection operation 68 memory map 23 memory space 294 memory space structure 22 mode data 67 m...

Page 314: ...t select register SEGR 246 serial data register SDR 179 serial I O function 170 serial input data register SIDR 211 serial input operation 183 serial input operation at completion of 184 serial input program example for 192 serial mode control register 1 SMC1 205 serial mode control register 2 SMC2 213 serial mode register SMR 176 serial output data register SODR 212 serial output operation 181 se...

Page 315: ...ion of 216 UART program example for 220 V vector table area addresses FFC0H to FFFFH 25 W watchdog timer control register WDTC 115 watchdog timer function 112 watchdog timer block diagram of 113 watchdog timer note on using 118 watchdog timer operation of 116 watchdog timer program example for 119 ...

Page 316: ...302 INDEX ...

Page 317: ...E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC 8L 8 BIT MICROCONTROLLER MB89950 950A Series HARDWARE MANUAL July 2002 the first edition Published FUJITSU LIMITED Electronic Devices Edited Technical Information Dept ...

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