14
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface PCB
Design Guideline
5.2.
Pull-out wiring condition
This section shows the example of mounting the bypass capacitor for the high frequency noise removal.
Be sure to meet the following pull-out wiring conditions to reduce the inductance value by wiring and to
reduce the noise. If it doesn't meet these conditions, widen the wire width as much as possible, and shorten
the wire length.
Note 1) There is no problem even if the Chip on Via method without the pull-out wiring is used.
Figure 5-1 Example of mounting a bypass capacitor
Pu
ll-out
w
irin
g
Pu
ll-out
w
irin
g
Pu
ll
-out
w
irin
g
Pu
ll
-out
w
irin
g
Power
PAD
GND
PAD
PAD
PAD
PAD
PAD
PAD
PAD
1mm
GND
via
Power
via
Bypass capacitor
(mounted on
Ln layer
）
L1 layer MB86R11 PAD
1mm
L1 layer pull-out wiring
L1
~
Ln layer via
Ln layer pull-out wiring
Bypass capacitor PAD
［
Pull-out wiring conditions
］
Wire width (W): over 0.3mm
Wire length (L): under 0.71mm
* Average value of all pull-out
wiring
Wire width
(W)
W
ire
le
ngt
h
(L
)
Wi
re
l
engt
h
(L
)
PAD
L1 layer MB86R12 PAD
