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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB86R12 Application Note
DDR3 Interface PCB
Design Guideline
4.7.
Wiring topology
This section illustrates the recommended wiring topology of each group.
4.7.1.
Wiring topology diagram of MCK_Group
Figure 4-5 Wiring topology diagram of MCK_Group
DDR3_
SDRAM
For DQ[15:0]
MB86R12
DDR3_
SDRAM
For DQ[31:16]
L2
(15.5mm
~
15.9mm)
No limit
3 9
Ω
L1 (24.8mm
~
25.3mm)
RON: 40[
Ω]
- In wiring, the L1/L8 layer is assumption.
- Wire length doesn't contain the length of the via.
Signal name
Length of wiring "L1 + L2" [mm]
MCK/MXCK 40.7±1 (Differential and equal-length)
Wire length of each CLK signal
39
Ω
VSS
0.1μF
