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FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB86R12 Application Note
DDR3 Interface PCB

Design Guideline

4. Signal design restrictions (DDR3 interface part)

This chapter describes the signal wiring design restrictions for the DDR3 interface part.

4.1.

Definition of signal line group

In order to make the requirements for wiring configurations described further on in this document easier to
understand, the DDR3 interface signals are classified into the groups listed below.

Table 4-1 DDR3 interface signal grouping

Wiring

preferential

order

Group name

Pin name of MB86R12

1

MCK_Group

MCK, MXCK

2

MDQS0_Group

MDQS0, MXDQS0

MDQS1_Group

MDQS1, MXDQS1

MDQS2_Group

MDQS2, MXDQS2

MDQS3_Group

MDQS3, MXDQS3

3

MDQ0_Group

MDQ0~MDQ7, MDM0

MDQ1_Group

MDQ8~MDQ15, MDM1

MDQ2_Group

MDQ16~MDQ23, MDM2

MDQ3_Group

MDQ24~MDQ31, MDM3

4

MCNTL_Group

MCKE, MXCS, MODT

5

MCMD_Group

MA0~MA14, MBA0~MBA2, MXCAS, MXRAS, MXWE

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Summary of Contents for MB86R12

Page 1: ...FUJITSU SEMICONDUCTOR CONFIDENTIAL MB86R12 Application Note DDR3 Interface PCB Design Guideline November 2011 The 1 0 edition ...

Page 2: ......

Page 3: ...lt from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high ...

Page 4: ...ii MB86R12 Application Note DDR3 Interface PCB Design Guideline FUJITSU SEMICONDUCTOR CONFIDENTIAL Revision History Date Ver Contents 2011 11 29 1 0 Newly issued ...

Page 5: ...ing restrictions 5 4 3 Resistance 5 4 4 Terminal resistance Damping resistance Wire length 6 4 5 Wiring gap Crosstalk 7 4 6 ZQ ODT setting 8 4 7 Wiring topology 9 4 7 1 Wiring topology diagram of MCK_Group 9 4 7 2 Wiring topology diagram of MDQSx_Group 10 4 7 3 Wiring topology diagram of MDQx_Group 11 4 7 4 Wiring topology diagram of MCNTL_Group MCMD_Group 12 5 Power system design restrictions 13 ...

Page 6: ......

Page 7: ...e PCB Design Guideline 1 Floor plan Figure 1 1 shows the reference example of the floor plan of MB86R12 and connected DDR3 SDRAM devices Figure 1 1 Reference example of the floor plan of MB86R12 and DDR3 SDRAM devices 27mm 9mm 27mm 32mm 6mm 9mm MB86R12 10mm 15 5mm SDRAM SDRAM ...

Page 8: ...f CLK L3 and L6 are used as wiring layer of DQS DQ and CMD ADD L2 and L5 are used as power layer L4 and L7 are used as GND layer Conductor thickness Insulator thickness L1 43μm SIG copper foil 18mm plating 25mm L2 35μm Power L3 35μm SIG L4 35μm GND L5 35μm Power L6 35μm SIG L7 35μm GND L8 43μm SIG copper foil 18mm plating 25mm Resist thickness 40μm 100μm 150μm 150μm 100μm 150μm 150μm 100μm 40μm In...

Page 9: ...e differences concerning I O quality which may require your attention However all I O characteristics should be checked as could differ Even if you use the device s listed below you must refer to the specifications provided by the DRAM manufacturer for the confirmation of details e g operating temperature conditions etc Table 3 1 Recommended DDR3_SDRAM Manufacturer Product name IBIS model name Dri...

Page 10: ...cribed further on in this document easier to understand the DDR3 interface signals are classified into the groups listed below Table 4 1 DDR3 interface signal grouping Wiring preferential order Group name Pin name of MB86R12 1 MCK_Group MCK MXCK 2 MDQS0_Group MDQS0 MXDQS0 MDQS1_Group MDQS1 MXDQS1 MDQS2_Group MDQS2 MXDQS2 MDQS3_Group MDQS3 MXDQS3 3 MDQ0_Group MDQ0 MDQ7 MDM0 MDQ1_Group MDQ8 MDQ15 MD...

Page 11: ...MDQS0_Group and MDQ0_Group MDQS1_Group and MDQ1_Group MDQS2_Group and MDQ2_Group MDQS3_Group and MDQ3_Group There are no restrictions to the number of layer transfer vias for other signals but use a minimum possible When using meander wiring layouts for signal delay crosstalk may occur and the delay value reduced therefore having wider spacing between wirings is recommended The recommended wire sp...

Page 12: ...wire length list No Group name External terminal resistance value Rt Damping resistance value Rd Wire length from MB86R12 output to SDRAM input Internal group approved wire length variation 1 MCK_Group 39Ω 2 0 1μF capacitor 1 Refer to 4 7 1 N A Refer to 4 7 1 Meet the conditions of 4 7 1 2 MDQSx_Group N A N A Refer to 4 7 2 Meet the conditions of 4 7 2 3 MDQx_Group N A N A Refer to 4 7 3 Meet the ...

Page 13: ...s should be over 300µm Figure 4 3 Gap for wiring of other signal groups 3 Differential wiring signals of MCK_Group and MDQSx_Group should use a wiring gap of over 500µm to other signals If it is difficult to guarantee a gap above 500µm separate the wire from other signals using a GND area However please take the consequent decrease of the wiring impedance into consideration Figure 4 4 Gap for wiri...

Page 14: ...tput impedance of MB86R12 I O RON ZQ setting of MB86R12 MCK_Group 40Ω Perform the ZQ calibration and set it automatically MDQSx_Group 48Ω MDQx_Group 48Ω MCNTL_Group 60Ω MCMD_Group 60Ω Table 4 4 shows the recommended ODT setting conditions for MDQSx_Group and MDQx_Group signals Table 4 4 ODT setting conditions Operating condition MB86R12 DDR3_SDRAM Write to DDR3_SDRAM Off 60Ω Read from DDR3_SDRAM 4...

Page 15: ...ology diagram of MCK_Group Figure 4 5 Wiring topology diagram of MCK_Group DDR3_ SDRAM For DQ 15 0 MB86R12 DDR3_ SDRAM For DQ 31 16 L2 15 5mm 15 9mm No limit 3 9Ω L1 24 8mm 25 3mm RON 40 Ω In wiring the L1 L8 layer is assumption Wire length doesn t contain the length of the via Signal name Length of wiring L1 L2 mm MCK MXCK 40 7 1 Differential and equal length Wire length of each CLK signal 39Ω VS...

Page 16: ...gth of wiring L1 mm MDQS0 MXDQS0 30 9 3 Differential and equal length MDQS1 MXDQS1 31 5 3 Differential and equal length MDQS2 MXDQS2 30 5 3 Differential and equal length MDQS3 MXDQS3 28 7 3 Differential and equal length DDR3_ SDRAM MB86R12 RON 48 Ω ODT 40 Ω Driver strength 34 Ω ODT 60 Ω L1 Wire length of each DQS signal In wiring the L3 L6 layer is assumption Wire length doesn t contain the length...

Page 17: ...gth of MDQS0_Group Average value 1 1 2 MDQ23 Wire length of MDQS2_Group Average value 2 5 2 MDM1 Wire length of MDQS1_Group Average value 2 5 2 MDM3 Wire length of MDQS3_Group Average value 4 7 2 MDQ8 Wire length of MDQS1_Group Average value 4 4 2 MDQ24 Wire length of MDQS3_Group Average value 3 2 2 MDQ9 Wire length of MDQS1_Group Average value 3 1 2 MDQ25 Wire length of MDQS3_Group Average value ...

Page 18: ...g topology diagram of MCNTL_Group MCMD_Group DDR3_ SDRAM For DQ 15 0 MB86R12 DDR3_ SDRAM For DQ 31 16 0 6mm or less L1 L8 layer L1 31 0mm 44 7mm 39Ω RON 60 Ω L2 17 1mm 17 4mm No limit Wire length from MB86R12 to SDRAM at the farthest position 48 7mm 62 7mm In wiring the L3 L6 layer is assumption Wire length doesn t contain the length of the via 0 6mm or less VTT DDRVDE 2 ...

Page 19: ...capacitors Remarks 0 1µF DDRVDE 1 5V 18 For DDR3 interface VSS 0V If capacity is a value close to 0 1µF 0 22µF etc for instance the bypass capacitor can be used Place the 0 1µF capacitor as close as possible to the power GND pins of MB86R12 refer to 5 2 Pull out wiring condition For the 0 1µF capacitor we recommend the use of ceramic capacitors of under size 1005 1 0mm 0 5mm In addition use low ES...

Page 20: ...shorten the wire length Note 1 There is no problem even if the Chip on Via method without the pull out wiring is used Figure 5 1 Example of mounting a bypass capacitor Pull out w iring Pull out w iring Pull out wiring Pull out wiring Power PAD GND PAD PAD PAD PAD PAD PAD PAD 1mm GND via Power via Bypass capacitor mounted on Ln layer L1 layer MB86R11 PAD 1mm L1 layer pull out wiring L1 Ln layer via...

Page 21: ......

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