Fuji Electric Faldic-a RYS-R Series, User Manual

Page: 160 / 291

5-48
MHT260a (Engl.)
■
LS-Z phase pulse
The LS-Z phase pulse can be selected at on/off of SEL0, SEL1, SEL2.
This can be read out at the ON edge of the read command.
Read/rewrite data (select)
SEL2 SEL1 SEL0 IQ area (Upper line: 0 to 7W, Lower line: 8 to 15W)
LS-Z phase current pulse value ON ON ON
-
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
LS-Z phase pulse
(Low order word PC ß Amplifier)
1
LS-Z phase pulse
(High order word PC ß Amplifier)
2
−
3
−
4
−
5 − − − − − − −
6
−
CSEL
2
CSEL
1
CSEL
0
−
7
RDY
W
PSET
CPU
ready
ALM
Data
error Address
error
− − − − − − − −
Rewrite
end
Read
end
8
−
9 −
10
−
11
−
12 −
13
− − − − − − − −
14
−
SEL2 SEL1 SEL0
−
15
RUN FWD REV RST START ORG X1 VEL0 VEL1 DIR
−
− − −
Rewrite
command
Read
command
・
LS-Z phase pulse
Word position Setting range
Address 0
Address 1
LS-Z phase pulse can be stored in 2 word. The positive value only is allowed.
The min. value 1 is corresponds to 1 [pulse].
Address 2
to
Address 5
(disabled)
Address 6 The status of SEL2, SEL1 and SEL0 are stored (CSEL2, CSEL1, CSEL0).
Address 7 (information on each bit is always valid.)
Address 8
to
Address 13
(disabled)
Address 14 LS-Z phase pulse is specified using SEL2 to SEL0.
Address 15 Bit 0 is read command (ON edge).
(command of each bit is always valid.)
The timing of rewrite end and read end is as same as basic para. and sytem para..