PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
Freescale Semiconductor
9
Debug
3.5
I
2
C Clock
The I
2
C clock rate is determined by a ratio set in the I2CFDR register. Refer to the MPC8555ERM.
3.6
L2 Cache and CPM Clocks
The clock rate for the L2 Cache and the CPM is the same as the CCB clock frequency.
3.7
Local Bus Clock Outputs
The local bus clock outputs LCLK[0:2] are derived from the CCB clock. By default the LCLKn frequency
is CCB clock frequency divided by eight. However, by appropriately setting the System Clock Divider
parameter in the Clock Ratio Register (LCRR[CLKDIV]), the LCLKn frequency can be configured as
shown in
.
3.8
PCI Clock Input
There are two modes for PCI clock input—synchronous mode and asynchronous mode. In synchronous
mode the input clock for the PCI interfaces on the MPC8555E and the MPC8541E is, by default, the
system clock (SYSCLK input). In asynchronous mode each PCI (PCI1, PCI2) interface can be configured
to use a separate PCI clock input unrelated to the SYSCLK input. The PCI clock mode is configured during
POR by TSEC2_TXD1, and TSEC2_TXD0 signals.
3.9
TSEC Reference Clock Input
This signal is not used for MII mode. When any other mode is used in the TSEC interface, the gigabit
transmit 125 MHz reference clock EC_GTX_CLK125 must be supplied. This signal must be generated
externally with a crystal or oscillator, or it can sometimes be provided by the PHY. In GMII, RGMII, RTBI
or TBI mode, EC_GTX_CLK125 is a 125 MHz input into the TSEC and is used to generate all
125-MHz-related signals and clocks.
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Debug
This section describes the PowerQUICC III reset sequence and recommendations for the system.
Table 5. Local Bus Clock Divider Options
LCRR[CLKDIV]
LCLKn Frequency
0010
CCB Clock / 2
0100
CCB Clock / 4
1000 (Default)
CCB Clock / 8
All other values
Reserved
