Freescale Semiconductor PowerQUICC III MPC8541E, Manuallines

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PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
Freescale Semiconductor 5
Power
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the V
DD
core supply, then the port pins on the MPC8555E and MPC8541E CPMs
may drive a logic-one or -zero during power-up.
Table 2 lists the current maximum ratings for the power supplies. Supplies must not exceed these absolute
maximum ratings. However, during normal operation, use of the Recommended Operating Conditions
table in the hardware specification is recommended. Any information in the relevant hardware
specification supersedes information in
Table 2 .
2.4 Power Planes
Each V
DD
pin should be provided with a low-impedance path to the board power supply. Similarly, each
ground pin should be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on-chip. The capacitor leads and associated printed circuit traces connecting to chip V
DD
and ground should be kept to less than half an inch per capacitor lead.
2.5 Decoupling
Due to large address and data buses and high operating frequencies, the PowerQUICC III can generate
transient power surges and high-frequency noise in its power supply, especially while driving large
capacitive loads. This noise must be prevented from reaching other components in the PowerQUICC III
system, and the PowerQUICC III itself requires a clean, tightly regulated source of power. Therefore, you
should place at least one decoupling capacitor at each V
DD
, GV
DD
, LV
DD
, OV
DD
, and pins of the
PowerQUICC III. These decoupling capacitors should receive their power from separate V
DD
, GV
DD
,
LV
DD
, OV
DD
, and GND power planes in the PCB, utilizing short traces to minimize inductance.
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part. These capacitors should have a value of 0.01 or 0.1 µF. To minimize lead inductance, only ceramic
SMT (surface mount technology) capacitors should be used. In addition, several bulk storage capacitors
should be distributed around the PCB, feeding the V
DD
, GV
DD
, LV
DD
, and OV
DD
planes, to enable quick
recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series
resistance (ESR) rating to ensure the quick response time necessary. They should also be connected to the
power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330
µF. Simulation is strongly recommended to minimize noise on the power supplies before proceeding into
the PCB design and manufacturing stage of development.
Table 2. Maximum Voltage Ratings
Type Name Block (V) (Vmax)
Core Vdd — 1.2 1.32
PLL AVdd Core PLL, Platform PLL, CPM PLL, PCI1, PCI2 1.2 1.32
I/O GVdd DDR 2.5 3.63
I/O LVdd TSEC 2.5 / 3.3 2.75 / 3.63
I/O OVdd CPM, LBIU, DMA, MII-mgt, PIC1,PCI2,
I
2
C
3.3 3.63